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Signal and Data Type Support

HDL Coder™ supports code generation for Simulink® signal types and data types with a few special cases.

Buses

If your DUT or other blocks in your model have many input or output signals, you can create bus signals to improve the readability of your model. A bus signal or bus is a composite signal that consists of other signals that are called elements.

You can generate HDL code for designs that use virtual and nonvirtual buses. For example, you can generate code for designs that contain:

  • DUT subsystem ports connected to buses.

  • Simulink and Stateflow® blocks that support buses and HDL code generation.

Supported Blocks with Buses

Bus-capable blocks are blocks that can accept bus signals as input and produce bus signals as outputs. For a list of bus-capable blocks that Simulink supports, see Bus-Capable Blocks. HDL Coder supports code generation for bus-capable blocks in the HDL Coder block library. For more details, see the "HDL Code Generation" section of each block page. The supported blocks include:

In addition, subsystems, models, and these user-defined functions support buses for simulation and HDL code generation:

Bus Support Limitations

Buses are not supported in the IP Core Generation workflow. In addition, you cannot generate code for designs that use:

  • A Black box model reference connected to a bus.

  • A bus input to a Delay block with nonzero Initial condition.

Enumerations

You can generate code for Simulink, MATLAB®, or Stateflow enumerations within your design.

Requirements

  • The enumeration values must be monotonically increasing.

  • The enumeration strings must have unique names and must not use a reserved keyword in the Verilog® or VHDL language.

  • If your target language is Verilog, all enumeration member names must be unique within the design.

Restrictions

Enumerations at the top-level DUT ports are not supported with the following workflows or verification methods:

  • IP Core Generation workflow

  • FPGA Turnkey workflow

  • Simulink Real-Time FPGA I/O workflow

  • Customization for the USRP Device workflow

  • FPGA-in-the-loop

  • HDL Cosimulation

Matrices

You can use matrix types with these blocks in your design. For more details, see the "HDL Code Generation" section of each block page.

HDL Coder Block LibrarySupported blocks

Discontinuities

These blocks are supported:

Discrete

These blocks are supported:

HDL Floating Point Operations

The Rounding Function block is supported.

HDL Operations

All blocks in this library are supported.

HDL RAMs

Blocks in this library are not supported.

HDL Subsystems

Blocks in this library are not supported.

Logic and Bit Operations

These blocks are supported:

Lookup Tables

Blocks in this library are not supported.

Math Operations

These blocks are supported:

Model Verification

All blocks in this library are supported.

Model-Wide Utilities

The DocBlock is supported. The Model Info block does not support matrix data types.

Ports & Subsystems

The Subsystem block is supported.

Signal Attributes

These blocks are supported:

Signal Routing

These blocks are supported:

Sources

These blocks are supported:

Sinks

These blocks are supported:

User-Defined FunctionsThe MATLAB Function block is supported.

The code generator does not support matrix types at the interfaces of the Subsystem that you generate HDL code for. Use a Reshape block to convert the matrix input to a 1-D array at the interface. Inside the Subsystem, use another Reshape block that converts the 1-D array back to the matrix type with the dimensionality that you specified.

Unsupported Signal and Data Types

  • Arrays stored in row-major layout are not supported for HDL code generation

  • Variable-size signals are not supported for code generation.

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