Mux

Combine input signals of same data type and numeric type into virtual vector

• Library:

• Simulink / Commonly Used Blocks

  Simulink / Signal Routing

  HDL Coder / Commonly Used Blocks

  HDL Coder / Signal Routing

Description

The Mux block combines its inputs into a single vector output. An input can be a scalar or vector signal. All inputs must be of the same data type and numeric type. For information about creating and decomposing vectors, see Mux Signals.

The elements of the vector output signal take their order from the top to bottom, or left to right, input port signals. See Port Location After Rotating or Flipping for a description of the port order for various block orientations.

The nonvirtual components of a virtual signal are called regions. A virtual signal can contain the same region more than once. For example, if the same nonvirtual signal is connected to two input ports of a Mux block, the block outputs a virtual signal that has two regions. The regions behave as they would if they had originated in two different nonvirtual signals, even though the resulting behavior duplicates information.

Note

Simulink^® provides several techniques for combining signals into a composite signal. For more information, see Types of Composite Signals.

Ports

Input

Port_1 — Accept nonbus vector signal to extract and output signals from

real or complex values of any nonbus data type supported by Simulink

Port that accepts the input nonbus vector signal from which to extract and output signals.

Output

Port_1 — Output signals extracted from input vector signal

nonbus signal with real or complex values of any data type supported by Simulink

Output signals extracted from the input vector. The output signal ports are ordered from top to bottom. See Port Location After Rotating or Flipping for a description of the port order for various block orientations.

Parameters

Number of inputs — Inputs

2 (default) | scalar | vector | cell array | comma-separated list of signal names

Specify the number of input signals. You can also specify signal names and sizes. Use one of these formats.

Format	Block Behavior
Scalar	Specifies the number of inputs to the Mux block. When you use this format, the block accepts scalar or vector signals of any size. Simulink assigns each input the name signalN, where N is the input port number.
Vector	The length of the vector specifies the number of inputs. Each element specifies the size of the corresponding input. A positive value specifies that the corresponding port can accept only vectors of that size. For example, [2 3] specifies two input ports of sizes 2 and 3, respectively. If an input signal width does not match the expected width, an error message appears. A value of -1 specifies that the corresponding port can accept scalars or vectors of any size.
Cell array	The length of the cell array specifies the number of inputs. The value of each cell specifies the size of the corresponding input. A scalar value N specifies a vector of size N. A value of -1 means that the corresponding port can accept scalar or vector signals of any size.
Signal name list	You can enter a list of signal names separated by commas. Simulink assigns each name to the corresponding port and signal. For example, if you enter position,velocity, the Mux block has two inputs, named position and velocity.

Tip

If you specify a scalar for the Number of inputs parameter and all of the input ports are connected, as you draw a new signal line close to input side of a Mux block, Simulink adds a port and updates the parameter.

Programmatic Use

Block Parameter: Inputs

Type: scalar, vector, cell array, signal name list

Values: number, vector of port numbers, cell array, or list of signal names

Default: {'2'}

Display option — Displayed block icon

bar (default) | nonesignal

By default, the block icon is a solid bar of the block foreground color. To display the icon as a hollow bar containing input signal names, select signals. To display the icon as a box containing the block type name, select none.

Programmatic Use

Block Parameter: DisplayOption

Type: character vector

Values: 'bar' 'signals' 'none''bar'

Default: 'bar'

Model Examples

Vehicle Suspension Model

Model a simplified half-car model that includes an independent front and rear vertical suspension. The model also includes body pitch and bounce degrees of freedom. The example provides a description of the model to show how simulation can be used to investigate ride characteristics. You can use this model in conjunction with a powertrain simulation to investigate longitudinal shuffle resulting from changes in throttle setting.

Open Model

Block Characteristics

Data Types	Boolean | double | enumerated | fixed point | integer | single
Direct Feedthrough	yes
Multidimensional Signals	no
Variable-Size Signals	no
Zero-Crossing Detection	no

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

Actual data type or capability support depends on block implementation.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

Restrictions

Buses are not supported for HDL code generation.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion

Design and simulate fixed-point systems using Fixed-Point Designer™.

Actual data type or capability support depends on block implementation.