Sign

Indicate sign of input

• Library:

• Simulink / Math Operations

  HDL Coder / HDL Floating Point Operations

  HDL Coder / Math Operations

• 

Description

Block Behavior for Real Inputs

For real inputs, the Sign block outputs the sign of the input:

Input	Output
Greater than zero	1
Equal to zero	0
Less than zero	–1

For vector and matrix inputs, the block outputs a vector or matrix where each element is the sign of the corresponding input element, as shown in this example:

Block Behavior for Complex Inputs

When the input u is a complex scalar, the block output matches the MATLAB^® result for:

sign(u) = u./ abs(u)

When an element of a vector or matrix input is complex, the block uses the same formula that applies to scalar input, as shown in this example:

Ports

Input

Port_1 — Input signal

scalar | vector | matrix

Input signal whose sign will determine the output.

The block supports complex input signals only for floating-point data types, double and single.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point
Complex Number Support: Yes

Output

Port_1 — Output signal

scalar | vector | matrix

Output signal that is the sign of the input signal.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point
Complex Number Support: Yes

Parameters

Enable zero-crossing detection — Enable zero-crossing detection

on (default) | Boolean

Select to enable zero-crossing detection. For more information, see Zero-Crossing Detection.

Programmatic Use

Block Parameter: ZeroCross

Type: character vector, string

Values: 'off' | 'on'

Default: 'on'

Sample time — Specify sample time as a value other than -1

-1 (default) | scalar | vector

Specify the sample time as a value other than -1. For more information, see Specify Sample Time.

Dependencies

This parameter is not visible unless it is explicitly set to a value other than -1. To learn more, see Blocks for Which Sample Time Is Not Recommended.

Programmatic Use

Block Parameter: SampleTime

Type: character vector

Values: scalar or vector

Default: '-1'

Model Examples

Modeling a Fault-Tolerant Fuel Control System

Combine Stateflow® with Simulink® to efficiently model hybrid systems. This type of modeling is particularly useful for systems that have numerous possible operational modes based on discrete events. Traditional signal flow is handled in Simulink while changes in control configuration are implemented in Stateflow. The model described below represents a fuel control system for a gasoline engine. The system is highly robust in that individual sensor failures are detected and the control system is dynamically reconfigured for uninterrupted operation.

Open Model

Friction Model with Hard Stops

Model friction one way in Simulink®. The two integrators in the model calculate the velocity and position of the system, which is then used in the Friction Model to calculate the friction force.

Open Model

Block Characteristics

Data Types	Boolean | double | fixed point | integer | single
Direct Feedthrough	yes
Multidimensional Signals	no
Variable-Size Signals	no
Zero-Crossing Detection	yes

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.