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Content Feed
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How to initialize Dual rate Dual port ram?
RAM System object can be used as a block in Simulink and it supports Initial Value. The HDL library browser that ships with ...
How to initialize Dual rate Dual port ram?
RAM System object can be used as a block in Simulink and it supports Initial Value. The HDL library browser that ships with ...
대략 22시간 전 | 0
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Why did I receive an error message：ISim engine error: Failed to Load up XSI.
Please try running with Vivado 2022.1. You can see our supported software in the documentation at: https://www.mathworks.com/hel...
Why did I receive an error message：ISim engine error: Failed to Load up XSI.
Please try running with Vivado 2022.1. You can see our supported software in the documentation at: https://www.mathworks.com/hel...
3일 전 | 0
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제출됨
HDLCoder Design Patterns and Examples
Several tutorials in this submission show how to generate HDL from MATLAB code, Simulink models, and Simscape models.
7일 전 | 다운로드 수: 9 |
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Simulink port annotations do not appear with HDL definition of wire/reg
I have reported the issue to the development team. As a workaround consider right-cliking on the port, choose port propert...
Simulink port annotations do not appear with HDL definition of wire/reg
I have reported the issue to the development team. As a workaround consider right-cliking on the port, choose port propert...
12일 전 | 0
| 수락됨
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How ro restore a fixed-pointed and saved model to its unfixed state?
>>I want to change some fuctions on its unfixed state. Do you mean the restore step in the Fixed-Point Tool failed for you a...
How ro restore a fixed-pointed and saved model to its unfixed state?
>>I want to change some fuctions on its unfixed state. Do you mean the restore step in the Fixed-Point Tool failed for you a...
12일 전 | 0
답변 있음
DSP Builder HDL Import Design Example error
Please reach out to tech support. The error is coming from HDL Cosimulation block (probably you are using a HDL Verifer Cosimu...
DSP Builder HDL Import Design Example error
Please reach out to tech support. The error is coming from HDL Cosimulation block (probably you are using a HDL Verifer Cosimu...
15일 전 | 0
답변 있음
ip core generation stuck at hdl code generation step
Would you be able to share the MATLAB Code and the Project file? Please reach out to tech support for help.
ip core generation stuck at hdl code generation step
Would you be able to share the MATLAB Code and the Project file? Please reach out to tech support for help.
16일 전 | 0
답변 있음
HDL Coder, Assertion failed: B:\matlab\src\cgir_hdl\dom_pir_core\dutinfo.cpp:101:portIdx < m_inportMap.size()
Can you share the model? This is not an expected error. Please reach out to MathWorks tech support and they can help you with ...
HDL Coder, Assertion failed: B:\matlab\src\cgir_hdl\dom_pir_core\dutinfo.cpp:101:portIdx < m_inportMap.size()
Can you share the model? This is not an expected error. Please reach out to MathWorks tech support and they can help you with ...
19일 전 | 0
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implementing complex multiplication in simulink
For HDL Code Generation you can use the Simulink and MATLAB function examples shown below. These examples use FPGA/ASIC fri...
implementing complex multiplication in simulink
For HDL Code Generation you can use the Simulink and MATLAB function examples shown below. These examples use FPGA/ASIC fri...
22일 전 | 1
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HDL Coder cannot run HDL Code Generation
If you want to run a set of steps you need to right-click on the step and run to the task. It will run all the steps leading...
HDL Coder cannot run HDL Code Generation
If you want to run a set of steps you need to right-click on the step and run to the task. It will run all the steps leading...
26일 전 | 0
답변 있음
How to generate testbench for a model whose input signals come from matlab workspace?
"Generate HDL Testbench" works on a subsystem with some stimulus and response and not the whole model. Mark the DUT "model/sub...
How to generate testbench for a model whose input signals come from matlab workspace?
"Generate HDL Testbench" works on a subsystem with some stimulus and response and not the whole model. Mark the DUT "model/sub...
27일 전 | 1
| 수락됨
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When I try to check Subsystem Compatibility, the report says"cannot coonect to model, please try Update Diagram".
The error message is showing that during code generation process, HDL Coder is unable to compile the model. If you are able to ...
When I try to check Subsystem Compatibility, the report says"cannot coonect to model, please try Update Diagram".
The error message is showing that during code generation process, HDL Coder is unable to compile the model. If you are able to ...
30일 전 | 0
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답변 있음
HDL Workflow Advisor Error
If you can share the model please add the attachment. If open the Sample time legend and do not see continuous sample time (0) f...
HDL Workflow Advisor Error
If you can share the model please add the attachment. If open the Sample time legend and do not see continuous sample time (0) f...
대략 1개월 전 | 0
답변 있음
Error - periodic sample time - Pixels to Frame
The pixelIn and controlIn should be operating at the same rate when using pixel streaming based interface. https://www.mathwo...
Error - periodic sample time - Pixels to Frame
The pixelIn and controlIn should be operating at the same rate when using pixel streaming based interface. https://www.mathwo...
대략 1개월 전 | 0
답변 있음
HDL Workflow Adviser Error: Abnormal exit: Invalid Simulink object name: stateflow
This error is unrelated to the name of the chart. Probably a corrupt model or an internal issue during HDL Code generation. If...
HDL Workflow Adviser Error: Abnormal exit: Invalid Simulink object name: stateflow
This error is unrelated to the name of the chart. Probably a corrupt model or an internal issue during HDL Code generation. If...
대략 1개월 전 | 0
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HDL Code Generation Check Report - word width error
You have to constrain the operator wordlength to be within 128 bit limit for HDL Code generation.
HDL Code Generation Check Report - word width error
You have to constrain the operator wordlength to be within 128 bit limit for HDL Code generation.
대략 1개월 전 | 0
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How to use proprietary IPS with HDL coder?
When generating RTL from Simulink model or MATLAB algorithm, there are several ways to integrate custom HDL IP with HDL Coder ge...
How to use proprietary IPS with HDL coder?
When generating RTL from Simulink model or MATLAB algorithm, there are several ways to integrate custom HDL IP with HDL Coder ge...
대략 1개월 전 | 0
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design and implement adaptive filter for noise signals cancellation in ecg and heartbeat
https://www.mathworks.com/matlabcentral/fileexchange/35328-simulink-model-for-fetal-ecg-extraction-hdl-compatible-algorithm
design and implement adaptive filter for noise signals cancellation in ecg and heartbeat
https://www.mathworks.com/matlabcentral/fileexchange/35328-simulink-model-for-fetal-ecg-extraction-hdl-compatible-algorithm
대략 1개월 전 | 0
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Error Cannot find a valid sample time for the model. Continuous signal rates are not supported in native floating-point mode.
This is error is auto-resolved in HDL Coder starting R2023a release. https://www.mathworks.com/help/hdlcoder/release-notes.htm...
Error Cannot find a valid sample time for the model. Continuous signal rates are not supported in native floating-point mode.
This is error is auto-resolved in HDL Coder starting R2023a release. https://www.mathworks.com/help/hdlcoder/release-notes.htm...
대략 1개월 전 | 1
답변 있음
Error in converting function into fixed point using HDL Coder
Getting Started with Targeting Xilinx Zynq Platform This example shows how to use the hardware-software co-design workflow to b...
Error in converting function into fixed point using HDL Coder
Getting Started with Targeting Xilinx Zynq Platform This example shows how to use the hardware-software co-design workflow to b...
대략 1개월 전 | 0
답변 있음
Is there any plan to support Vivado ML for the HDL Coder tools?
Vivado ML Editions is the FPGA EDA tool suite from AMD/Xilinx based on machine-learning optimization algorithms, as well as ad...
Is there any plan to support Vivado ML for the HDL Coder tools?
Vivado ML Editions is the FPGA EDA tool suite from AMD/Xilinx based on machine-learning optimization algorithms, as well as ad...
대략 1개월 전 | 0
답변 있음
Example HDL QAM : changing QAM 64 to QAM 256
It looks like you are stuck modifying the existing to QAM 256. Please reach out to tech support for additional guidance. They ca...
Example HDL QAM : changing QAM 64 to QAM 256
It looks like you are stuck modifying the existing to QAM 256. Please reach out to tech support for additional guidance. They ca...
대략 1개월 전 | 0
답변 있음
Can I use HDL Coder without a Vivado license in my machine?
HDL Coder generates synthesizable VHDL and Verilog code. You can use the target settings to customize the code for a specific ha...
Can I use HDL Coder without a Vivado license in my machine?
HDL Coder generates synthesizable VHDL and Verilog code. You can use the target settings to customize the code for a specific ha...
대략 1개월 전 | 0
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답변 있음
What are MIL, SIL, PIL, and HIL, and how do they integrate with the Model-Based Design approach?
“M”, “S”, “P” and “H” are all referring to the Controller. PIL uses the Controller Processor only (no I/O connectivity), HIL ...
What are MIL, SIL, PIL, and HIL, and how do they integrate with the Model-Based Design approach?
“M”, “S”, “P” and “H” are all referring to the Controller. PIL uses the Controller Processor only (no I/O connectivity), HIL ...
대략 1개월 전 | 0
답변 있음
Error: variable-size matrix type is not supported for HDL code
Variable dimensions are not synthesizable to hardware and hence not supported for HDL Code generation. >> mlhdlc_demo_setup...
Error: variable-size matrix type is not supported for HDL code
Variable dimensions are not synthesizable to hardware and hence not supported for HDL Code generation. >> mlhdlc_demo_setup...
대략 1개월 전 | 0
답변 있음
import hdl coder fails, why?
This is a limitaiton of importhdl feature. In general only subset of verilog is convertible to Simulink using this feature.
import hdl coder fails, why?
This is a limitaiton of importhdl feature. In general only subset of verilog is convertible to Simulink using this feature.
대략 2개월 전 | 0
답변 있음
I see the following error message in HDL Workflow Advisor
Can you share reproduction steps? Thanks
I see the following error message in HDL Workflow Advisor
Can you share reproduction steps? Thanks
대략 2개월 전 | 0
답변 있음
When using Simulink External Mode with an AXI4-Stream IIO Read block, if the timeout value is greater than zero, it cause the simulation time to be slower than actual time
The timeout behavior is expected, the timeout leads to overrun in the software task and so the time step will get out of sync wi...
When using Simulink External Mode with an AXI4-Stream IIO Read block, if the timeout value is greater than zero, it cause the simulation time to be slower than actual time
The timeout behavior is expected, the timeout leads to overrun in the software task and so the time step will get out of sync wi...
2개월 전 | 0
답변 있음
Issue in HDL Coder
t = 1:10; x = [4 8 6 -1 -2 -3 -1 3 4 5]; yc = movmean(x,5); plot(t,x,t,yc); The movemean fun...
Issue in HDL Coder
t = 1:10; x = [4 8 6 -1 -2 -3 -1 3 4 5]; yc = movmean(x,5); plot(t,x,t,yc); The movemean fun...
2개월 전 | 0
답변 있음
Issue in HDL Coder
Can you share the design, testbench and project files? Feel free to reach out to MathWorks tech support or DM me with the repro...
Issue in HDL Coder
Can you share the design, testbench and project files? Feel free to reach out to MathWorks tech support or DM me with the repro...
2개월 전 | 0
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