how to reduce Estimated Slice LUTs Utilization in FPGA code generation process.

Hello, I am working on generating a bitfile from a Simulink model. While converting, the Simulink model is using more slice LUTs (352,424 out of 203,800) and it is showing a utilization error. Is there any HDL configuration to reduce slice LUTs (such as using pipelining processes)?

My target device is PXIe-7858R.

Answer 1

[Kiran Kintali]

You may find these links helpful to reduce your area consumption on the hardware.

https://www.mathworks.com/help/hdlcoder/ug/resource-sharing-for-area-optimization.html

https://www.mathworks.com/help/hdlcoder/ug/resource-sharing-with-design-modifications.html

https://www.mathworks.com/help/hdlcoder/ug/iteratively-maximize-clock-frequency-using-speed-optimizations.html