Characterisation error in HDL code generation?

When generating RTL code for VHDL for an Artix-7 using FPGA-In-The-Loop, I'm met with these error messages and only the first section of the design is characterised. The critical path is given as 0ns.

'Error using hdlcoder.pirctx/buildCharacterizationData

Unexpected error during HDL Code Generation.

Contact [e-mail] with reproduction steps.

Assertion failed with debug message:

B:\matlab\src\cgir_hdl\target_analysis\ParameterizedDatabaseReader.cpp:101:paramChar

Error in characterization.readCharacterizationData

Error in slhdlcoder.HDLCoder/runPIRTransformAndCodegen

Error in slhdlcoder.HDLCoder/makehdl

Error in downstream.DownstreamIntegrationDriver/runGenerateRTLCodeAndTestbench

Error in runGenerateRTLCodeAndTestbench

Error in Simulink.ModelAdvisor/executeCheckCallbackFct

Error in Simulink.ModelAdvisor/run

Error in Simulink.ModelAdvisor/runCheck

Error in ModelAdvisor.Node/runTaskAdvisor'

[Steven Hatcher]

Hi Dylan,

1. What release are you using?
2. Are you specifying a custom timing database you generated using genhdltdb with TimingDatabaseDirectory?

Steven

Answer 1

[Kiran Kintali]

This is an unexpected error. What version of MATLAB are you using?

Can you share the model? Do not hesitate to reach out to tech support for a workaround. Thanks