In this SoC project example, the FPGA generates test data and process it in FPGA algorithm before passing it to processor using shared memory.
Open a new Simulink® model. Save the model as
soc_hwsw_fpga_sample.slx into the subfolder, named
referencedmodels, in the project folder.
On the Modelling tab, click Model
Settings. On the Configuration parameters
window, in the Hardware Implementation panel, set
Hardware board to
set Device vendor to
In the Solver panel, set Solver selection > Type to
OK to apply the changes and close the configuration
SoC Blockset™ requires that the FPGA reference models specify the intended deployment hardware, in this case an FPGA.
The signals for
rdCtrlOut must use bus signal types set to
When your FPGA model includes more than one IP, you must define each IP as a subsystem and connect the subsystems using a Stream Connector or Video Stream Connector block. For additional information, see Considerations for Multiple IPs in FPGA Model.
In the SoC Bus Creator block dialog mask, set Control
Test Source subsystem simulates a free-running counter.
Test Source subsystem and create the following
All data is valid and
Tlast, must produce a signal with
FPGA Algorithm subsystem simulates the multiplication
of streamed data. Open the
FPGA Algorithm subsystem and using
an Enabled Subsystem, Logical Operator, and Data Type Conversion blocks,
create the following system.
The Stream from FPGA to Processor Template, the FPGA subsystem uses a model variant to select between the sample based model developed in this section and a frame based model. The frame based model allows faster simulations but does not support code generation.