Using SoC Blockset™, you can model a simplified, streaming protocol in your model. Use HDL Coder™ to generate AXI4-Stream interfaces in the IP core.
When you want to generate an AXI4-Stream interface in your IP core, in your DUT interface, implement the following signals:
When you map scalar DUT ports to an AXI4-Stream interface, you can optionally model the following signals and map them to the AXI4-Stream interface:
Other protocol signals, such as:
When the Data signal is valid, the Valid signal is asserted.
The AXI4-Stream interfaces in your DUT can optionally include a Ready signal. In a Slave interface, the Ready signal enables you to apply back pressure. In a Master interface, the Ready signal enables you to respond to back pressure.
If you model the Ready signal in your AXI4-Stream interfaces, your Master interface ignores the Data and Valid signals one clock cycle after the Ready signal is deasserted. You can start sending Data and Valid signals once the Ready signal is asserted. You can send one more Data and Valid signal after the Ready signal is deasserted.
If you do not model the Ready signal, HDL Coder generates the signal and the associated back pressure logic.
For example, if you have a FIFO in your DUT to store a frame of data, to apply back pressure to the upstream component, you can model the Ready signal based on the FIFO Full signal.