The memory channel models the data transfer from FPGA to processor using shared external memory. The register channel models the control of FPGA logic from processor. You can both configure the FPGA logic and read the status of FPGA logic from processor. The following sections show how to create these channel connections.
Open the Memory
Controller block dialog mask. Set Number of
2. In the
Advanced tab, the Memory
Controller automatically inherits parameters from the
Hardware board specified in the model
Connect the pair of Memory
Controller burst ports,
burstDone, to the read and write burst request ports of
the Memory Channel block.
In the model, open the Memory
Channel block dialog mask. Set Channel type to
AXI4-Stream to Software via DMA. Set
Buffersize (bytes) to
and Number of buffers to
Add a Register
Channel block to the model and connect the block to the
FPGA subsystems as shown
in the following image.
Open the Register Channel block dialog mask. Add a new register with these properties.
Set Register write sample time to
FPGASSTime. Click OK. This sample
time is set in the file