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Memory and Register Channel Connections

The memory channel models the data transfer from FPGA to processor using shared external memory. The register channel models the control of FPGA logic from processor. You can both configure the FPGA logic and read the status of FPGA logic from processor. The following sections show how to create these channel connections.

Memory Channel Connection

  1. Open the soc_hwsw_top.slx model.

  2. Add a Memory Channel block and a Memory Controller block to the Memory area. Together, these blocks model the memory connection through DDR between the processor and FPGA sides of your application.

  3. Open the Memory Controller block dialog mask. Set Number of masters to 2. In the Advanced tab, the Memory Controller automatically inherits parameters from the Hardware board specified in the model configurations.

  4. Connect the pair of Memory Controller burst ports, burstReq and burstDone, to the read and write burst request ports of the Memory Channel block.

  5. In the model, open the Memory Channel block dialog mask. Set Channel type to AXI4-Stream to Software via DMA. Set Buffersize (bytes) to FrameSize*4 and Number of buffers to 6. Click OK.

Register Channel Connection

  1. Add a Register Channel block to the model and connect the block to the Processor and FPGA subsystems as shown in the following image.

  2. Open the Register Channel block dialog mask. Add a new register with these properties.

    RegisterDirectionData typeDimension
    configRegWriteuint81

    Set Register write sample time to FPGASSTime. Click OK. This sample time is set in the file soc_hwsw_init.m.

See Also

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