SoC Bus Creator
Convert control signals to bus
Libraries:
SoC Blockset /
Hardware Logic Connectivity
Description
The SoC Bus Creator block combines a set of signals into a bus. The block accepts control signals and outputs a bus.
You can configure this block to support multiple protocol interface types. Parameter and port configurations for this block vary based on your desired protocol interface type and mode of operation, as outlined in this table.
Protocol Interface Type | Mode of Operation | Parameter Configuration | Enabled Input Ports |
---|---|---|---|
Data stream | Read data stream | Set Control protocol to | ready |
Write data stream | Set Control protocol to | valid | |
tlast | |||
Pixel stream | Read video stream | Set Control protocol to | ready |
Write video stream | Set Control protocol to
| hStart | |
hEnd | |||
vStart | |||
vEnd | |||
valid | |||
Read video stream with frame sync | Set Control protocol to
| ready | |
fsync | |||
Random access read | Read data | Set Control protocol to
| rd_addr |
rd_len | |||
rd_avalid | |||
rd_dready | |||
Random access write | Write data | Set Control protocol to
| wr_addr |
wr_len | |||
wr_valid |
Examples
Ports
Input
Output
Parameters
Extended Capabilities
Version History
Introduced in R2019a