IP Core Generation

What Is IP Core Generation?

A semiconductor intellectual property core – often referred to as an IP core – is a reusable HDL component for an FPGA, SoC FPGA, or ASIC design.

IP Core Generation with MATLAB and Simulink

IP core generation using an AXI4 interface to write data to an IP core on target hardware. (See details for Intel and AMD)


In FPGAs and SoC FPGAs, IP cores act as building blocks that you can integrate into complete implementations using design tools such as Vivado® IP Integrator and ISE from AMD or Qsys from Intel. The AMBA® AXI version 4 AXI interconnect protocol – better known as AXI4 – has emerged as a standard protocol for memory-mapped and streaming data transfer.

Common workflows for IP core generation produce IP cores that comply with the AXI4 interface supported by AMD and Intel and also the AXI4-Lite and AXI4-Stream protocols for AMD® devices. You can integrate these custom IP cores into FPGA or SoC FPGA designs with AMD Vivado IP Integrator or with Qsys from Intel.

You can do IP core generation from MATLAB® code or Simulink® models. You can also use the IP core generation workflow in HDL Coder™ with the C/C++ code generation features in Embedded Coder® in an automated hardware-software workflow that targets AMD Zynq® SoCs and Intel® SoC FPGAs.

For additional details, see HDL Coder™.

See also: FPGA design and SoC codesign, Embedded Coder, HDL Coder, motor control design with Simulink, AMD Zynq support from Simulink, Intel SoC FPGA support from HDL Coder