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Vision Processing for FPGA, Part 4: Targeting a Lane Detection Design to a Xilinx Zynq Device

From the series: Vision Processing for FPGA

Jack Erickson, MathWorks

Vision processing applications often use System-on-Chip (SoC) devices such as those from Xilinx^® and Intel^®, which allow computationally-intensive tasks running on the hardware to work closely with innovative applications running in software. Learn how to convert data types to fixed point and generate optimized HDL with AXI bus interfaces using the HDL Coder^™ IP Core Generation Workflow. Details include:

Visualizing and adjusting fixed-point data types
Using the HDL Workflow Advisor to generate VHDL
Setting up and using the IP Core Generation Workflow, mapping the inputs to AXI Stream for Video and the outputs to AXI4 Lite interfaces
Determining the required clock frequency for processing this video input format
Generating VHDL and analyzing the results

Product Focus

Series: Vision Processing for FPGA

Part 1: Vision Processing FPGA and ASIC Hardware Considerations Learn about some of the key factors to consider when targeting a vision processing algorithm to FPGA or ASIC hardware.

Part 2: Workflow from a Frame-Based Algorithm to a Pixel-Streaming Implementation Reuse MATLAB vision processing scripts and algorithms to verify a Simulink hardware implementation.

Part 3: Hardware Design of a Lane Detection Algorithm Learn about the hardware implementation techniques used in the Vision HDL Toolbox lane detection example.

Part 4: Targeting a Lane Detection Design to a Xilinx Zynq Device Generate optimized fixed-point HDL to target the lane detection example to FPGA fabric.

Part 5: Hardware-Software Prototyping of a Lane Detection Design Prototype a hardware-software implementation of an automated driving application using the Computer Vision Toolbox Support Package for Xilinx Zynq-Based Hardware.

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Part 5: Hardware-Software Prototyping of a Lane Detection...

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