FPGA HDL 코드 생성

Simscape 모델에서 실시간 FPGA 배포를 위한 HDL 코드 생성

빠른 샘플 시간 요구 사항이 있는 모델이나 서브시스템은 FPGA 시뮬레이션의 이점을 얻을 수 있습니다. HDL Coder™가 있으면, Simscape 플랜트 모델을 HDL 구현 모델로 변환하고, 이를 사용하여 FPGA에 배포할 HDL 코드를 생성할 수 있습니다. Simscape 모델이나 서브시스템을 FPGA에 배포하려면 다음을 수행하십시오.

sschdladvisor 함수를 사용하여 Simscape HDL Workflow Advisor를 실행합니다. 그러면 HDL 구현 모델 생성을 위한 과정이 안내됩니다.
HDL Workflow Advisor 툴을 사용하여 구현 모델을 HDL 코드로 변환합니다.
Simulink^® Real-Time™을 사용하여 HDL 코드를 FPGA에 배포합니다.

모델 합성을 통해, 달성 가능한 하드웨어 시간 스텝을 예측할 수 있습니다.

Steps of generating HDL code from Simscape models and deploying the code on hardware.

함수

`sschdladvisor`	Open Simscape HDL Workflow Advisor
`simscape.findNonlinearBlocks`	Check model for blocks with nonlinear equations
`sschdl.updateRuntimeParameters`	Generate updated tunable parameter data file for Simscape model (R2024a 이후)
`sschdl.generateOptimizedModel`	Replace Simscape switches and converter blocks with dynamic switches optimized for FPGA deployment (R2024a 이후)

도움말 항목

Get Started with Simscape Hardware-in-the-Loop Workflow (HDL Coder)
Simscape™ Hardware-in-the-Loop workflow modeling guidelines and restrictions.
Linearize a Simscape Model to Prepare for HDL Code Generation
Learn how to linearize a model that uses the Backward Euler solver for HDL deployment.
Generate HDL Code for FPGA Platforms from Simscape Models
Learn how to convert Simscape models to HDL Code for FPGA Deployment.
Generate Optimized HDL Implementation Model from Simscape (HDL Coder)
Optimize area and timing of HDL implementation model generated from Simscape by using HDL Coder optimizations.
Generate and Validate HDL Code for Simscape Model (HDL Coder)
Generate HDL code from Simscape switched linear models.
Generate HDL Code for Simscape Models with Multiple Networks (HDL Coder)
Split a large Simscape network into multiple networks and generate HDL implementation model.
Generate HDL Code for Simscape Three-Phase PMSM Drive Containing Averaged Switch (HDL Coder)
Generate HDL code and synthesize the results for a three-phase PMSM Simscape models with converter blocks that have averaged switches and deploy onto the FPGAs.
Simulate Large Time Steps Using Trapezoidal Rule Solver for Real-Time FPGA Deployment (HDL Coder)
Generate HDL code for a Simscape model by using the Trapezoidal Rule solver and deploy it onto a Speedgoat^® FPGA I/O module.
Generate HDL Code for Simscape Models by Using Dynamic Switch Approximation (HDL Coder)
Generate HDL code and synthesize the results for a three-phase PMSM drive using Dynamic Switch Approximation method.
Improve FPGA Sampling Frequency of HDL Implementation Model Generated from Simscape Algorithm (HDL Coder)
Oversampling in generated HDL implementation model, and relation between model sample time and sample time of original Simscape algorithm.
Validate HDL Implementation Model to Simscape Algorithm (HDL Coder)
Validate and resolve simulation mismatch between Simscape algorithm and HDL implementation model.
Synthesis Results for Simscape Hardware-in-the-Loop Workflow (HDL Coder)
Access synthesis results for Simscape hardware-in-the-loop workflow example models.