System on Chip (SoC)
R2026bCreate SoC or application-specific SoC Simulink® models of an application. Use preconfigured model templates or follow the SoC model guidelines. SoC Blockset™ for AMD model templates provide design patterns and implement best practices for creating an SoC model. The suggested workflow shows the process to combine processor software, user-specified programmable logic, shared memory systems, and on-chip peripherals to create an SoC model of an application. Use analysis functions and tools to estimate the resources that application uses. Compare different architectures to understand design tradeoffs in partitioning between processor software and programmable logic.
The blockset exports reference designs for SoCs, ASICs, and FPGAs using AMD® design tool. Automatically generate hardware and software code, and then execute the application on an SoC device by using the SoC Builder tool. Code generation requires the HDL Coder™ product, Embedded Coder® product, or both.
Apps
| Embedded Linux Explorer | Connect to hardware, monitor resources, and control applications running embedded Linux (Since R2023a) |
| Frequency Planner | Tune transceiver configuration and view frequency responses for RF devices (Since R2026a) |
Tools
| SoC Builder | Build, load, and execute SoC model on SoC, FPGA, and MCU boards |
| FPGA IP Block Generator | Generate Simulink block for FPGA IP core (Since R2023a) |
Functions
xilinxsoclib | Open the SoC Blockset for AMD block library |
socModelAnalyzer | Estimate number of operations in Simulink model |
socFunctionAnalyzer | Estimate number of operations in MATLAB function |
socAlgorithmAnalyzerReport | Open algorithm analysis report |
socTaskSchedulability | Determine whether set of tasks can be scheduled for specified core assignments (Since R2022b) |
socCreateModel | Creates a skeleton SoC Blockset for AMD model for task set (Since R2022b) |
socSDCardImage | Get SD card image path (Since R2024a) |
socWriteSDCardImage | Write board-specific SD card image files to host SD card location (Since R2024a) |
Objects
socModelBuilder | Build, load, and execute SoC model on SoC and FPGA boards (Since R2023a) |
Model Settings
Topics
Processor, Programmable Logic, and Memory
- SoC Blockset Model Structure
Top level structure of SoC model. - Use Template to Create SoC Model
Create SoC models using Simulink project templates.
- Create an SoC Project Application
Step-by-step instructions and guidelines for creating an SoC project and models for an SoC application.
- STEP 1: Project and Top-Level Model
- STEP 2: Software and Task Management on Processor
- STEP 3: User Logic on FPGA
- STEP 4: Memory and Register Channel Connections
- STEP 5: Simulation and Analysis
- SoC Targeting Workflows
Choose between IP core generation workflow and SoC modeling and generation workflow for deploying your design on an SoC device.
- Generate SoC Software Model
Generate Simulink software models using the IP core generation workflow. - Custom Hardware Board Configuration
Develop an SoC application model with a custom board configuration.
Application-Specific SoCs
- Use Template to Create SoC Model
Create SoC models using Simulink project templates.
Architecture and Analysis
- Using the Algorithm Analyzer Report
Navigate details of the report generated by thesocModelAnalyzerorsocFunctionAnalyzerfunction.
Troubleshooting
Build Error When FPGA or Processor Model Not Detected
Unsupported mode in when generating SoC design using SoC Builder.
Build Error for Rapid Accelerator Mode
Unsupported simulation mode in SoC Blockset for AMD models and projects.
Featured Examples
Streaming Data from Hardware to Software Using AMD SoC Devices
A systematic approach to design the data-path between hardware logic (FPGA) and embedded processor using SoC builder workflow.
Streaming Data from Software to Hardware Using AMD SoC Devices
Design the data-path from an embedded processor to hardware logic (FPGA) using SoC builder workflow. Design and simulate the entire application comprising of FPGA and processor algorithms, memory interface, and task scheduling to meet the system requirements. Then, validate the design on hardware by generating code from the model and implementing it on a System-on-Chip (SoC) device.
Triggering Software Tasks by FPGA Interrupts Using AMD SoC Devices
Model an algorithm partitioned between hardware and software. The hardware IP is implemented in FPGA fabric, and triggers a software task implemented in the embedded processor. Design, simulate, and implement a complete design on SoC hardware.
Estimate Number of Operators for MATLAB Algorithm
Estimate the number of arithmetic operators in an algorithm written in MATLAB®. Analyze a radix 2 FFT algorithm and generate reports showing operator usage.
Compare FIR Filter Implementations Using socModelAnalyzer
Analyze and compare different implementations of a Simulink® algorithm based on the number of arithmetic operations. Use the socModelAnalyzer function provided by SoC Blockset™ for AMD product to generate reports that show the number of operators for different implementations of a FIR Filter using static and runtime execution.
Systems Engineering Approach for SoC Applications
Design a sample signal detector application on a System on Chip (SoC) platform using a systems engineering approach. The workflow in this example maps the application functions onto the selected hardware architecture.
Derive RF Data Converter Configuration Using Frequency Planner App
Use Frequency Planner app to derive RF data converter configuration based on required signal specifications.
