Peripherals
R2026bCreate Simulink® models with simulations of the peripherals available on SoC devices. Connect peripherals to the software algorithms and hardware user-logic subsystems of an SoC application model. Add asynchronous communication and data capture simulation to the model using I/O device blocks with event message signals. Capture data from peripherals on hardware boards in deployed models to use in simulation.
Blocks
 | DIP Switch | Connect signals attached to DIP switches on hardware board |
 | IO Pin | Connect model signals to I/O pins on hardware board (Since R2026a) |
 | LED | Connect signals attached to LEDs on hardware board |
 | Push Button | Connect signals attached to push buttons on hardware board |
 | IO Data Sink | Record, output, or terminate input message |
 | IO Data Source | Play back recorded data |
 | TCP Read | Receive TCP/IP packets from remote host over TCP/IP network |
 | TCP Write | Send TCP/IP packets to remote host over TCP/IP network |
 | UDP Read | Receive UDP packets from remote host |
 | UDP Write | Send UDP packets to remote host |
 | UDP Read (HOST) | Receive UDP packets on local host computer from remote host |
 | UDP Write (HOST) | Send UDP packets from host computer to remote host |
 | Audio Capture | Capture audio samples from an input audio device and send to an algorithm |
 | Audio Capture Interface | Simulate capture of sample from audio stream on hardware |
 | Audio Playback | Playback audio samples from an algorithm to an output audio device |
 | Audio Playback Interface | Simulate audio output device on a hardware board |
 | Video Capture | Capture video from input video device and send to algorithm |
 | Video Capture Interface | Simulate capture of images from video stream on hardware |
 | Video Display | Display image samples from an algorithm to an output video device |
 | Video Display Interface | Simulate display of images to video screen on device |
 | Video Stream FIFO | Control backpressure between hardware logic and upstream video interface |
 | Video Stream Connector | Connect two IPs with video streaming interfaces |
 | Video Test Sink | Receive continuous video stream data |
 | Video Test Source | Generate continuous video stream data |
 | AD936x Receiver | Receive data from AD936x-based Zynq radio hardware (Since R2024b) |
 | AD936x Transmitter | Send data to AD936x-based Zynq radio hardware (Since R2024b) |
 | AD936x Data Read | Read data from AD936x-based Zynq radio hardware (Since R2024b) |
 | AD936x Data Write | Write data to AD936x-based Zynq radio hardware (Since R2024b) |
 | HDMI Rx | Convert video stream to YCbCr 4:2:2 pixel stream |
 | HDMI Tx | Convert YCbCr 4:2:2 pixel stream to video frame |
 | RF Data Converter | Provide RF data path interface to hardware logic |
 | ADC To Vector | Convert concatenated 16-bit ADC input samples to vector outputs |
 | Vector To DAC | Convert vector inputs to concatenated 16-bit DAC output samples |
 | RFDC Bus Creator | Convert control signals into RF Data Converter real-time interface-compatible bus (Since R2022a) |
 | RFDC Bus Selector | Convert RF Data Converter real-time interface-compatible bus into control signals (Since R2022a) |
 | Aurora 64B66B | Provide high-speed serial communication using Xilinx Aurora interface (Since R2023a) |
 | AXI4-Stream IIO Read (HOST) | Read DDR memory buffer from IP core device into simulation model |
 | AXI4-Stream IIO Write (HOST) | Write arrays to DDR memory buffer of IP core device from simulation model |
 | AXI4-Register IIO Read (HOST) | Read memory-mapped registers into simulation model |
 | AXI4-Register IIO Write (HOST) | Write data to memory-mapped registers from a simulation model |
 | Memory IIO Read | Read from a shared memory region into simulation model (Since R2023a) |
 | Memory IIO Write | Write from simulation model to a shared memory region (Since R2023a) |
Objects
socHardwareBoard | Connection to SoC hardware board |
DataRecorder | Data recording session for specified SoC hardware board |
soc.iosource | Input source on SoC hardware board |
socFileReader | File reader |
socAXIManager | Read and write memory locations on hardware board from MATLAB |
socIPCore | Create object to represent IP core running on FPGA board |
socMemoryProfiler | Retrieve and display memory performance data |
Tools
| Hardware Mapping | Map memory, tasks, and peripherals in a model to hardware board configurations (Since R2022b) |
| FPGA IP Block Generator | Generate Simulink block for FPGA IP core (Since R2023a) |
Functions
xilinxsoclib | Open the SoC Blockset for AMD block library |
Model Settings
Topics
Design and Simulation
- Use Memory and I/O Device Data in Processor Simulation
Use memory and I/O device data in SoC Blockset™ for AMD processor model simulations.
Build and Measurement
- Record Data from Hardware I/O Devices
Connect and record I/O device data from network attached hardware boards.
Featured Examples
Record I/O Data from AMD SoC Device
Record real-world data from an AMD® SoC device for use in simulation.
Simulate with I/O Data Recorded from AMD SoC Device
Use recorded real-world data from an AMD® SoC device in simulation.
RF Data Recording and Playback for RFSoC Devices
Capture real-world RF data from RFSoC devices, and then use this data in MATLAB® and Simulink for simulation and analysis.
Validate RF Data Converter Configuration
Validate RF data converter (RFDC) configuration in simulation.
Transmit and Receive Tone Using AMD RFSoC Device - Part 1 System Design
Design and simulate data path using SoC Blockset for AMD on Xilinx® RFSoC device.
Transmit and Receive Tone Using AMD RFSoC Device - Part 2 Deployment
Implement and verify design using SoC Blockset for AMD on Xilinx RFSoC device.
Transmit and Receive Tones Using AD9361 Dual-Channels
Design, simulate, and deploy dual-channel application system with AD9361 RF card using SoC Blockset for AMD on Xilinx Zynq® UltraScale+™ MPSoC ZCU102 Evaluation Kit.
QPSK Transmit and Receive Using Zynq and FMCOMMS2/3/4
Simulate and deploy quadrature phase-shift keying (QPSK) transmit and receive algorithm using SoC Blockset for AMD.
Frequency Hopping Using Xilinx RFSoC Device
Design and implement frequency hopping algorithm using Xilinx RF Data Converter numerically controlled oscillator (NCO) real time ports.
Detect and Capture Wideband Radar Signal Using AMD RFSoC Device
Build, simulate, and deploy wideband radar signal detection and capture system using SoC Blockset for AMD on Xilinx RFSoC device.
Import Custom FPGA IP into SoC Blockset Design
Import FPGA IP and integrate it into SoC Blockset for AMD design.
Minimum Variance Distortionless Response Beamformer Using AMD RFSoC Device
Deploy minimum variance distortionless response algorithm on AMD® RFSoC device.
Multi-Tile Synchronization Using AMD RFSoC Device
Implement and use multi-tile synchronization using RF Data Converter block on AMD RFSoC device.
Derive RF Data Converter Configuration Using Frequency Planner App
Use Frequency Planner app to derive RF data converter configuration based on required signal specifications.
