Speed and Area Optimization
For your target hardware, generate HDL code that meets timing and area requirements by using speed and area optimizations. Area optimizations reduce resource usage of your design. Speed optimizations improve the timing of your design on the target FPGA so that your design runs at higher frequencies by optimizing the critical path. To learn more about each type of optimization in HDL Coder™, see Speed and Area Optimizations in HDL Coder.
- Optimization Basics
Hierarchy flattening, delay balancing, validation model, constrained overclocking, feedback loop highlighting
- Area Optimization
RAM mapping, resource sharing, streaming
- Speed Optimization
Critical path estimation and reduction, pipeline register insertion, loop unrolling, automated iterative clock frequency optimization