Pipelining

R2026b

Optimize speed by using adaptive pipelining, clock-rate pipelining, and distributed pipelining

Improve the timing and increase the clock speed of your design for a target FPGA or SoC device by reducing the critical path. You can reduce the critical path by using different pipelining methods, such as adaptive pipelining, clock-rate pipelining, and distributed pipelining.

Functions

`hdlcoder.optimizeDesign`	Automatic iterative HDL design optimization
`hdlcoder.supportedDevices`	Show supported target hardware and device details
`coder.hdl.pipeline`	Insert pipeline registers at output of MATLAB expression

Classes

hdlcoder.OptimizationConfig hdlcoder.optimizeDesign configuration object

Model Settings

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Pipelining

Allow design delay distribution	Allow distributed pipelining and delay absorption optimizations to move design delays
Pipeline distribution priority	Priority for distributed pipelining and delay absorption optimizations
Clock-rate pipelining	Insert pipeline registers at faster clock rate than data rate
Allow clock-rate pipelining of DUT output ports	Pass the outputs from DUT at clock rate
Balance clock-rate pipelined DUT output ports	Synchronize DUT outputs while satisfying highest-latency requirements of outputs (Since R2022b)
Distributed pipelining	Enable pipeline register distribution
Use synthesis estimates for distributed pipelining	Use synthesis timing estimates to guide pipeline register insertion (Since R2022a)
Adaptive pipelining	Insert adaptive pipeline registers
Map lookup tables to RAM	Map lookup tables to block RAM

Blocks

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HDL Operations

	Serializer1D	Convert vector signal to scalar or smaller vectors
	Deserializer1D	Convert scalar stream or smaller vectors to vector signal
	Multiply-Accumulate	Perform a multiply-accumulate operation on the inputs
	Multiply-Add	Multiply-add combined operation

Topics

Adaptive Pipelining

Specify Adaptive Pipelining Settings
Automatic pipeline insertion based on the target device, target frequency, and multiplier word-lengths.
Design Patterns That Benefit from Adaptive Pipelining
For certain design patterns, you must enable the adaptive pipelining optimization to meet the timing requirements.
Optimize Clock Speed for MATLAB Code by Using Adaptive Pipelining
Use the adaptive pipelining optimization in HDL Coder™ to optimize clock speed for a MATLAB^® design.

Distributed Pipelining

Specify Distributed Pipelining Settings
Distributed pipelining settings, benefits and costs.
Distributed Pipelining Using Synthesis Timing Estimates
Use synthesis timing estimates for distributed pipelining to more accurately reflect how components function on hardware to better distribute pipelines and increase clock frequency for your target device.
Use Distributed Pipelining Optimization in Models with MATLAB Function Blocks
How to optimize HDL code for MATLAB Function blocks for speed by distributing design delays and generated pipeline stages.

Clock-Rate Pipelining

Clock-Rate Pipelining
Pipeline registers insertion at the faster clock-rate instead of the slower data rate.
Increase Clock Frequency Using Clock-Rate Pipelining
This example shows how to apply clock-rate pipelining to optimize slow paths in your design and thereby reduce latency, increase clock frequency and decrease area usage.

General

Pipelining MATLAB Code
Pipelining helps achieve a higher maximum clock rate by inserting registers at strategic points in the hardware to break the critical path.
Pipeline MATLAB Expressions
Insert registers at output of MATLAB expression.
Constrained Output Pipelining
Constrained output pipelining definition and use case.
Automatic Iterative Optimization
How automatic iterative optimization works, prerequisites and restrictions.

Related Information

Troubleshooting

Resolve Simulation Mismatch When Pipelining with a Feedback Loop Outside the DUT

Learn how to resolve simulation mismatch issues when using pipeline optimizations with feedback loops.

Featured Examples

Distributed Pipelining: Speed Optimization

Optimize a Simulink® design for speed by using the distributed pipelining optimization.

Open Script

Iteratively Maximize Clock Frequency by Using Speed Optimizations

Iteratively maximize the clock frequency for your model using various speed and area optimizations.

Open Script