IP Core Generation and Deployment
R2026bGenerate a reusable HDL IP core to design a system that you can deploy on hardware or a combination of hardware and software. Deploy your MATLAB® or Simulink® design:
As hardware and software on system-on-chip (SoC) platforms, such as AMD® Zynq®, Altera® SoC or Microchip SoC.
On standalone FPGA boards, such as an Altera FPGA or an AMD FPGA board.
On platforms that have a separate FPGA and processor, such as the Simulink Real-Time™ target machine with FPGA I/O boards.
If you are using an SoC platform or a platform that has a separate FPGA and processor, you can partition your design to generate hardware that targets the FPGA fabric and software that runs on the embedded processor of the target platform.
For more details on the workflow, see Targeting FPGA and SoC Hardware Overview. For more details on specific hardware platforms, see HDL Coder Supported Hardware.
Categories
- IP Core Generation Basics
Learn the basics of IP core generation
- Prepare Model for IP Core Generation
Prepare a model or MATLAB function for IP core generation
- Generate and Deploy IP Core
Generate portable HDL IP core with AXI interfaces. Deploy to off-the-shelf or custom FPGA and SoC platforms from AMD, Altera, Microchip, Speedgoat®, and others
- Run and Verify Generated IP Core
Prototype, simulate, and verify the generated IP core on your target FPGA device
- Configure IP Core for Software Interface
Configure a software interface model to connect your designed IP core and to deploy to the embedded processor of your target hardware
- IP Core Generation for Hardware-Software Deployment
Deploy and run hardware-software model on target hardware
- Deploy IP Core on Custom Hardware
Integrate generated IP core into a target SoC device, Speedgoat I/O module, or standalone FPGA board by defining a custom board and reference design
