General Optimizations
R2026bOptimize your design for a target FPGA or SoC device by applying optimizations such as hierarchy flattening, constrained overclocking, or feedback loop highlighting. Applying base optimizations helps to generate more hardware-efficient HDL code and properly simulate the generated code.
Topics
- Introduction to Optimizations in HDL Coder
Learn about speed and area optimizations and how to optimize your design.
- Enabling Optimizations in HDL Coder
Learn the settings that directly impact the speed and area of the generated HDL code.
- Find Feedback Loops
Highlight feedback loops that are inhibiting optimizations.
- Hierarchy Flattening
Flatten subsystem hierarchy to enable more extensive area and speed optimization.
- Optimization with Constrained Overclocking
Optimization with constrained overclocking and how it works.
- Subsystem Optimizations for Filters
Select resource sharing and pipeline optimization options.
- Generated Model and Validation Model
The generated model is a model created during HDL code generation that shows the HDL implementation architecture and includes latency.
- Use Synthesis Attributes to Map Adders to DSPs on FPGAs
Apply synthesis attributes to map adders to dedicated DSP slices for optimized FPGA implementation. (Since R2026a)
Featured Examples
HDL Optimizations Across MATLAB Function Block Boundary Using MATLAB Datapath Architecture
Apply optimizations inside and across MATLAB Function blocks with other Simulink® blocks.
Remove Redundant Logic and Unused Blocks in Generated HDL Code
Improve readability of generated HDL code and optimize area usage.
Optimize Unconnected Ports in HDL Code for Simulink Models
Optimize unused ports in generated HDL code in combination with redundant logic deletion.
Simplify Constant Operations and Reduce Design Complexity in HDL Coder
Area and timing optimizations that simplify constants and optimize mathematical operations.
