Main Content

Optimization Basics

Hierarchy flattening, delay balancing, validation model, constrained overclocking, feedback loop highlighting


Speed and Area Optimizations in HDL Coder

Learn about various speed and area optimizations and how to optimize your design.

Find Feedback Loops

Highlight feedback loops that are inhibiting optimizations.

Hierarchy Flattening

Flatten subsystem hierarchy to enable more extensive area and speed optimization.

Optimization with Constrained Overclocking

Optimization with constrained overclocking and how it works.

Delay Balancing

Insert matching delays along all data paths.

Generated Model and Validation Model

The generated model is an intermediate model that shows the HDL implementation architecture and includes latency.

Remove Redundant Logic and Unused Blocks in Generated HDL Code

Improve readability of generated HDL code and optimize area usage.

Optimize Unconnected Ports in HDL Code for Simulink Models

Optimize unused ports in generated HDL code in combination with redundant logic deletion.

Simplify Constant Operations and Reduce Design Complexity in HDL Coder

Area and timing optimizations that simplify constants and optimize mathematical operations.

Meet Timing Requirements Using Enable-Based Multicycle Path Constraints

Generate enable-based constraints for synthesis tools to meet timing requirements of multicycle paths in single clock mode.


Resolve Numeric Mismatch with Delay Balancing

Learn how to resolve numerical mismatch issues after HDL code generation.

Featured Examples