Main Content

addAXI4MasterInterface

Class: hdlcoder.ReferenceDesign
Package: hdlcoder

Add and define AXI4 Master interface

Syntax

addAXI4MasterInterface(InterfaceConnection',Interface_Connection)
addAXI4MasterInterface(InterfaceConnection',Interface_Connection,'TargetAddressSegments',Target_Address_Segments)
addAXI4MasterInterface(InterfaceConnection',Interface_Connection, Name,Value)
addAXI4MasterInterface(InterfaceConnection',Interface_Connection,'TargetAddressSegments',Target_Address_Segments, Name,Value)

Description

addAXI4MasterInterface(InterfaceConnection',Interface_Connection) adds and defines an AXI4 Master interface for an Intel® Qsys reference design.

addAXI4MasterInterface(InterfaceConnection',Interface_Connection,'TargetAddressSegments',Target_Address_Segments) adds and defines an AXI4 Master interface for a Xilinx® Vivado® reference design.

addAXI4MasterInterface(InterfaceConnection',Interface_Connection, Name,Value) adds and defines an AXI4 Master interface for an Intel Qsys reference design, with additional options specified by one or more Name,Value pair arguments.

addAXI4MasterInterface(InterfaceConnection',Interface_Connection,'TargetAddressSegments',Target_Address_Segments, Name,Value) adds and defines an AXI4 Master interface for a Xilinx Vivado reference design, with additional options specified by one or more Name,Value pair arguments.

Input Arguments

expand all

Name of the reference design port that is connected to the AXI4 Master interface, specified as a character vector.

Example: 'axi_interconnect_1/S01_AXI'

Target address segment of the Xilinx Vivado reference design, specified as a character vector. The format of the target address segment is {'SegmentName', low address, range}. You must use a power of 2 value for range.

Example: '{{'mig_7series_0/memmap/memaddr',hex2dec('40000000'),hex2dec('40000000')}}'

Tip

To add more than one AXI4 Master interface to your reference design, call the addAXI4MasterInterface method multiple times depending on the number of interfaces you want to add. For each additional interface, specify a unique InterfaceID.

Name-Value Arguments

Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Before R2021a, use commas to separate each name and value, and enclose Name in quotes.

Name of the AXI4 Master interface that you add to the reference design, specified as a character vector. If you create multiple AXI4 Master interfaces, make sure that you use unique names for each interface.

Example: 'AXI4 Master 1'

Specify whether you want the AXI4 Master interface to support a read channel as a Boolean.

Example: 'ReadSupport','true' specifies support for an AXI4 Master read interface connection.

Specify whether you want the AXI4 Master interface to support a write channel as a Boolean.

Example: 'WriteSupport','true' specifies support for an AXI4 Master write interface connection.

Maximum width for the Data signal that is transferred across the AXI4 Master interface, specified as an integer.

Example: 'MaxDataWidth',32 specifies maximum data width of 32 bits.

Width of the AXI4 Master interface read and write addresses, specified as an integer.

Example: 'AddrWidth',32 specifies an address size of 32 bits.

Default starting address of the AXI4 Master read interface, specified as an integer.

Example: 'DefaultReadBaseAddr',hex2dec('40000000') specifies hex2dec('40000000') as the starting read address.

Default starting address of the AXI4 Master write interface, specified as an integer.

Example: 'DefaultReadBaseAddr',hex2dec('41000000') specifies hex2dec('41000000') as the starting write address.

Version History

Introduced in R2017b