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hdlcoder.ReferenceDesign class

Package: hdlcoder

Reference design registration object that describes SoC reference design

Description

refdesign = hdlcoder.ReferenceDesign('SynthesisTool', toolname) creates a reference design object that you use to register a custom reference design for an SoC platform.

To specify the characteristics of your reference design, set the properties of the reference design object.

Use a reference design tool version that is compatible with the supported tool version. If you choose a different tool version, it is possible that HDL Coder™ is unable to create the reference design project for IP core integration.

Construction

refdesign = hdlcoder.ReferenceDesign('SynthesisTool',toolname) creates a reference design object that you use to register a custom reference design for an SoC platform.

Input Arguments

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Synthesis tool name, specified as a character vector.

Example: 'Altera Quartus II'

Properties

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Reference design name, specified as a character vector. In the HDL Workflow Advisor, this name appears in the Reference design dropdown list.

Example: 'Default system (Vivado 2015.4)'

Board associated with this reference design, specified as a character vector.

Example: 'Enclustra Mars ZX3 with PM3 base board'

One or more tool versions that work with this reference design, specified as a cell array of character vectors.

Example: {'2015.4'}

Example: {'13.7','14.0'}

One or more design constraint files, specified as a cell array of character vectors. This property is optional.

Example: {'MarsZX3_PM3.xdc'}

Example: {'MyDesign.qsf'}

One or more relative paths to files or folders that the reference design requires, specified as a cell array of character vectors. This property is optional.

Examples of required files or folders:

  • Existing IP core used in the reference design.

    For example, if the IP core, my_ip_core, is in the reference design folder, set CustomFiles to {'my_ip_core']

  • PS7 definition XML file.

    For example, to include a PS7 definition XML file, ps7_system_prj.xml, in a folder, data, set CustomFiles to {fullfile('data', 'ps7_system_prj.xml')}

  • Folder containing existing IP cores used in the reference design. HDL Coder only supports a specific IP core folder name for each synthesis tool:

    • For Altera® Qsys, IP core files must be in a folder named ip. Set CustomFiles to {'ip'}.

    • For Xilinx® Vivado®, IP core files, or a zip file containing the IP core files, must be in a folder named ipcore. Set CustomFiles to {'ipcore'}.

    • For Xilinx EDK, IP core files must be in a folder named pcores. Set CustomFiles to {'pcores'}.

Note

To add IP modules to the reference design, it is recommended to create an IP repository folder that contains these IP modules, and then use the addIPRepository method.

Example: {'my_ip_core'}

Example: {fullfile('data', 'ps7_system_prj.xml')}

Example: {'ip'}

Example: {'ipcore'}

Example: {'pcores'}

Specify the device tree file name. For an example that shows how to use different device tree file names when mapping the DUT ports to different AXI4-Stream channels, see Dynamically Create Master Only or Slave Only or Both Master and Slave Reference Designs.

Example: 'devicetree_axistream_iio.dtb'

Specify whether you want the parameter Insert JTAG MATLAB as AXI Master (HDL Verifier Required) to be displayed in the Set Target Reference Design task of the HDL Workflow Advisor. By default, this property value is set to true, and the parameter is displayed in the Set Target Reference Design task. After you enable this property, to specify whether you want the code generator to insert the JTAG MATLAB as AXI Master IP, use the JTAGMATLABasAXIMasterDefaultValue property. If you do not want the parameter to be displayed, set the property value to false.

This property is optional.

Example: 'false'

Specify whether you want the code generator to insert the JTAG MATLAB as AXI Master IP. The values that you specify are the choices for the Insert JTAG MATLAB as AXI Master (HDL Verifier Required) dropdown in the Set Target Reference Design task of the HDL Workflow Advisor. To specify insertion of the JTAG as AXI Master automatically, before you set this property to on, set the AddJTAGMATLABasAXIMasterParameter property to true.

This property is optional.

Example: 'on'

Specify the IP cache zip file to include in your project. When you run the IP Core Generation workflow in the HDL Workflow Advisor, the code generator extracts this file in the Create Project task. The Build FPGA Bitstream task reuses the IP cache, which accelerates reference design synthesis.

This property is optional.

Example: 'ipcache.zip'

Specify whether you want the code generator to report timing failures in the Build FPGA Bitstream task as warnings or errors. When you run the IP Core Generation workflow in the HDL Workflow Advisor, by default, the code generator reports any timing failures as error. If you have implemented the custom logic to resolve timing failures, you can specify these failures to be reported as warning instead of error. To learn more, see Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows.

This property is optional.

Example: 'hdlcoder.ReportTiming.Warning'

Methods

CallbackCustomProgrammingMethodFunction handle for custom callback function that gets executed during Program Target Device task in the Workflow Advisor
CustomizeReferenceDesignFcnFunction handle for callback function that gets executed before Set Target Interface task in the HDL Workflow Advisor
EmbeddedCoderSupportPackageSpecify whether to use an Embedded Coder support package
PostBuildBitstreamFcnFunction handle for callback function that gets executed after Build FPGA Bitstream task in the HDL Workflow Advisor
PostCreateProjectFcnFunction handle for callback function that gets executed after Create Project task in the HDL Workflow Advisor
PostSWInterfaceFcnFunction handle for custom callback function that gets executed after Generate Software Interface task in the HDL Workflow Advisor
PostTargetInterfaceFcnFunction handle for callback function that gets executed after Set Target Interface task in the HDL Workflow Advisor
PostTargetReferenceDesignFcnFunction handle for callback function that gets executed after Set Target Reference Design task in the HDL Workflow Advisor
addAXI4MasterInterfaceAdd and define AXI4 Master interface
addAXI4SlaveInterfaceAdd and define AXI4 slave interface
addAXI4StreamInterfaceAdd AXI4-Stream interface
addAXI4StreamVideoInterfaceAdd AXI4-Stream Video interface
addClockInterfaceAdd clock and reset interface
addCustomEDKDesignSpecify Xilinx EDK MHS project file
addCustomQsysDesignSpecify Altera Qsys project file
addCustomVivadoDesignSpecify Xilinx Vivado exported block design Tcl file
addIPRepositoryInclude IP modules from your IP repository folder in your custom reference design
addInternalIOInterfaceAdd and define internal IO interface between generated IP core and existing IP cores
addParameterAdd and define custom parameters for your reference design
validateReferenceDesignCheck property values in reference design object
Introduced in R2015a