photo

Steven Hatcher

Last seen: 7일 전 |  2022년부터 활동

Followers: 0   Following: 0

메시지

Team Lead for the HDL Coder Optimizations area.

Programming Languages:
C++, MATLAB, VHDL

통계

  • Knowledgeable Level 1
  • First Answer

배지 보기

Feeds

보기 기준

답변 있음
Need help understanding how vector adressing on the HDL Ram Blocks for Burst Read and Write
There is a new feature for the RAM System blocks in R2025a to control vector access behavior. You can try it out with the R2025a...

7일 전 | 0

답변 있음
HDL-Coder Delay Balancing in Feedback-Loop workaround
Hi Niklas, There is an optimization that can leverage a faster clock in regions of logic running at a slower rate. It looks lik...

대략 2년 전 | 0

| 수락됨

답변 있음
Enabled Subsystem produce hold without bypass
Hi Andrew, The only way this style of code can be generated which avoids creation of the by-pass register is to have a delay at...

2년 초과 전 | 0

답변 있음
Multiply and add not correctly mapping to a single DSP slice
Hi Justin, Are any of the adders using saturation or rounding logic that a Xilinx DSP48E1 would not natively support? Looking a...

2년 초과 전 | 0