Enabled Subsystem produce hold without bypass

I have a Simulink Enabled subsytem, with the input directly driving the output.

A previous HDL coder generation a few years ago using Matlab 2019b generated this code:

module Enabled_block

(CLK_DSP_DFT,

RST_DSP_DFT_N,

In1,

Enable,

Out1);

input CLK_DSP_DFT;

input RST_DSP_DFT_N;

input signed [21:0] In1; // sfix13

input Enable;

output signed [21:0] Out1; // sfix13

wire Enable_out2;

reg signed [21:0] In1_hold; // sfix13

assign Enable_out2 = Enable;

always @(posedge CLK_DSP_DFT or negedge RST_DSP_DFT_N)

begin : Out1_hold_process

if (RST_DSP_DFT_N == 1'b0) begin

In1_hold <= 22'sb0000000000000000000000;

end

else begin

if (Enable_out2) begin

In1_hold <= In1;

end

end

end

assign Out1 = In1_hold;

endmodule // Enabled_block

Using the same block with HDL coder on 2020a today I get this:

module Enabled_block

(CLK_DSP_DFT,

RST_DSP_DFT_N,

In1,

Enable,

Out1);

input CLK_DSP_DFT;

input RST_DSP_DFT_N;

input signed [12:0] In1; // sfix13

input Enable;

output signed [12:0] Out1; // sfix13

wire Enable_out2;

wire signed [12:0] In1_bypass; // sfix13

reg signed [12:0] In1_last_value; // sfix13

assign Enable_out2 = Enable;

always @(posedge CLK_DSP_DFT or negedge RST_DSP_DFT_N)

begin : Out1_bypass_process

if (RST_DSP_DFT_N == 1'b0) begin

In1_last_value <= 13'sb0000000000000;

end

else begin

if (Enable_out2) begin

In1_last_value <= In1_bypass;

end

end

end

assign In1_bypass = (Enable == 1'b0 ? In1_last_value :

In1);

assign Out1 = In1_bypass;

endmodule // Enabled_block

The current HDL code from 2020a has a bypass system put in place. I want the code generated from 2020a to match what was generated previously. I've tried everything I can find that I think would make a difference, but I can't get the bypass to go away and be left with just an enabled hold signal. I don't have access to the orgianal designer and person who generated the previous code.

Does anyone know how to get the bypass to go away?

Answer 1

[Steven Hatcher]

Hi Andrew,

The only way this style of code can be generated which avoids creation of the by-pass register is to have a delay at the output of the enabled subsystem. The code snippets you've pasted will actually have different latency as the by-pass register allows for immediate passthrough. If HDL Coder detects there is a delay at the output of the enabled subsystem, then it knows not to generate this by-pass logic and can instead absorb that delay to effectively be an enabled delay.

The above model with default settings generates the following Verilog code in the latest release.

module Enabled_Subsystem
          (clk,
           reset,
           enb,
           In1,
           Enable,
           Out1);


  input   clk;
  input   reset;
  input   enb;
  input   signed [12:0] In1;  // sfix13
  input   Enable;
  output  signed [12:0] Out1;  // sfix13


  wire enb_gated;
  reg signed [12:0] In1_hold;  // sfix13


  assign enb_gated = Enable && enb;

  always @(posedge clk or posedge reset)
    begin : Out1_hold_process
      if (reset == 1'b1) begin
        In1_hold <= 13'sb0000000000000;
      end
      else begin
        if (enb_gated) begin
          In1_hold <= In1;
        end
      end
    end



  assign Out1 = In1_hold;

endmodule  // Enabled_Subsystem

If all you are after is gating the clock for a delay, then I would recommend simplifying your modeling to just use enabled delay blocks and using the State Control block at the top level of your model. With this State Control block set to Synchronous, it changes Simulink semantics for enabled and resettable logic to be more hardware friendly. You only need to add this State Control block once and it will apply to all levels of hierarchy below it. Using this modeling style will also avoid generating an extra HDL file for an empty subsystem.

https://www.mathworks.com/help/hdlcoder/ref/statecontrol.html

module Subsystem2
          (clk,
           reset,
           clk_enable,
           Enable,
           In2,
           ce_out,
           Out1);


  input   clk;
  input   reset;
  input   clk_enable;
  input   Enable;
  input   signed [12:0] In2;  // sfix13
  output  ce_out;
  output  signed [12:0] Out1;  // sfix13


  wire enb;
  reg signed [12:0] Delay_out1;  // sfix13


  assign enb = clk_enable;

  always @(posedge clk or posedge reset)
    begin : Delay_process
      if (reset == 1'b1) begin
        Delay_out1 <= 13'sb0000000000000;
      end
      else begin
        if (enb && Enable) begin
          Delay_out1 <= In2;
        end
      end
    end



  assign Out1 = Delay_out1;

  assign ce_out = clk_enable;

endmodule  // Subsystem2

I hope this information helps. I've attached the model for convenience.

Regards,

Steven Hatcher