Set up HDL verifier
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how can i fix this problem?
PS: I work with MATLAB 2019b, Quartus Prime 18.1 & FPGA cyclone IV GX.
답변 (1개)
YP
2022년 11월 21일
0 개 추천
The command line window shows "Expected programming file not generated".
You may need to check the project log see why the bit file gen failed.
카테고리
도움말 센터 및 File Exchange에서 FPGA, ASIC, and SoC Development에 대해 자세히 알아보기
2021년 1월 16일
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