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Sampling rate conversion issues in HDL coder

조회 수: 2(최근 30일)
Muhammad Rizwan
Muhammad Rizwan 2020년 10월 30일
답변: Kiran Kintali 2020년 11월 2일
Hi ,
I am trying to generate HDL code for the file attached.
I am trying to make a state machine which takes data at slow data rate and outputs at higher rate with some zero padding too.
Issue arise when I am forced to insert rate transition block at the input port of the state maschine(subsystem1).
when rate transition block is inserted then code is generated which redundent 1 bit registers requirement.
Is there any way to get rid of rate transition block but maintain the fucntionality too.
note:
load mat file before execution.

답변(2개)

Aman Vyas
Aman Vyas 2020년 11월 2일
Hi,
Since mostly block design operate on a single clock and thus clock in hdl coder is mostly linked to sample time in simulink. If you have two blocks connected to each other with different sample times, " sample time mismatch" would pop up. To avoid the sample time mismatch we generally use "rate transition block" to bring both the blocks sample time equal by upsampling and downsampling depending upon the application since then both of them can be collected to common clock.
If you wish to keep separate clocks you can make separate blocks and finally integrate using top module from top to bottom. Delays are inserted to match the sampling time and hence that wouldnt count to redundancy.
Hope it helps!

Kiran Kintali
Kiran Kintali 2020년 11월 2일
See attached QPSK Tx, Rx example that works with HDL Coder.
You can read through instructions in QPSKTxRxHDLExample.m on how to model in Simulink for this comms application.

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