SIL Testing Issue with NXP S32K3xx Hardware Board

Hello,

I have encountering an issue while attempting to create a SIL test harness for a model using the NXP S32K3xx hardware board. The error message "Error: The model is configured to create a SIL block, which is not supported for the selected hardware board. To resolve this, search for 'Create block' in the Configuration Parameters dialog box and set it to 'None' or 'PIL'" persists, even though the 'Create block' setting is already set to 'None'.

Model and Hardware Configuration Details:

• Hardware Board: NXP S32K3xx

Steps Taken to Troubleshoot:

1. Verified 'Create Block' Setting: Double-checked the 'Configuration Parameters' dialog box to ensure that the 'Create block' setting is indeed set to 'None'.

Tried this but still getting the same error.

i have attached an image of configuration parameter of our model and the error message for reference.

[Sumukh]

Hi @Abhijeet Kate,

Can you please provide the complete model being used here?

You can refer to the following points to try to identify the issue:

• Please note that subsystem model test harnesses do not support SIL verification, as stated in the following documentation: https://www.mathworks.com/help/releases/R2023b/sltest/ug/select-test-harness-properties-for-your-task.html#bun8a9w
• Kindly refer to the following documentation that specifes the workflow to perform SIL unit tests on atomic subsystems: https://www.mathworks.com/help/releases/R2023b/ecoder/ug/unit-test-subsystem-code-with-silpil-manager.html
• Target-specific (NXP, in this case) custom-code in the model that is not portable for execution on the development computer can lead to build errors. You can refer to the following documentation for SIL simulations to understand more about the limitations for SIL: https://www.mathworks.com/help/releases/R2023b/ecoder/ug/sil-and-pil-simulation-limitations.html#mw_0756ee83-0e45-469c-964a-c60354c06971
• The hardware implementation settings should be configured to allow for SIL compilation on the development computer, as specified in the following documentation: https://www.mathworks.com/help/releases/R2023b/ecoder/ug/software-and-processor-in-the-loop-sil-and-pil-simulation.html#d126e253047