The obtained FPGA (Hardware-in-the-loop) output waveform is inconsistent with Simulink simulation results.
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We combined Xilinx Zynq-7000 ZC702 Evaluation Kit and SImulink for HIL (Hardware-in-the-loop) simulation. The specific process is as follows: 1. Transform the power electronic model built in Simulink into a state-space model. 2. Run the state space model through HDL workflow to generate bit flow, and select IPcore mode. 3. Download the bitstream to the development board. Finally run and find the obtained FPGA output waveform is inconsistent with Simulink simulation results.