ip core generation stuck at hdl code generation step
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i have to convert function to ip using hdl coder but while converting it stuck at HDL code generation
1.the ouput Q port has 12*12 matrix, so in HDL code genetaion i have enabled frame to sample conversion
still am facing issues but i opted Generic ASIC/FPGA it generated a .v (verilog) file
could please help me out where am going wrong or do i have enable any other things
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Kiran Kintali
2023년 5월 15일
Would you be able to share the MATLAB Code and the Project file?
Please reach out to tech support for help.
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Angela Cuadros Castiblanco
2023년 5월 31일
Hello Prashanthi,
In general, matrix ports at the DUT interface are not supported in the IP core generation workflow unless Frame to Sample conversion is enabled. However, generating an IP core using frame to sample conversion is not supported for the MATLAB to HDL workflow as specified in the limitations listed in:
If you have access to Simulink, you can try generating an IP core from a Simulink model with a MATLAB function block, for an example see:
Alternatively, you can manually serialize the output of your design and map the scalar ports of the streaming output to AXI4-Stream interfaces and generate an IP core. For an example see:
mlhdlc_demo_setup('heq')
Hope that helps!
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