Design and implement sample rate conversion for an LTE receiver front end. The model is compatible with the Wireless HDL Toolbox™ receiver reference applications, and supports HDL code generation with HDL Coder™.

Filtered OFDM (F-OFDM) applies a filter to the symbols after the IFFT in the transmitter to improve bandwidth while maintaining the orthogonality of the complex symbols. This example implements a transmitter F-OFDM for HDL code generation. The example shows how to go from a MATLAB® reference model to an HDL-optimized Simulink® model. It includes converting from double to fixed-point types, and minimizing the resource use of the design on an FPGA.

Implement a variable-size FFT using a single FFT core.

The workflow to measure the BER of the Wireless HDL Toolbox™ LTE Turbo Decoder block using parsim to parallelize the simulations across EbNo points. This approach can be used to accelerate other Monte Carlo simulations.

The implementation of an additive white Gaussian noise (AWGN) generator that is optimized for HDL code generation and hardware implementation. The hardware implementation of AWGN accelerates the performance evaluation of wireless communication systems using an AWGN channel. In this example, the Simulink® model accepts signal-to-noise ratio (SNR) values as inputs and generates Gaussian random noise along with valid signal. The example supports SNR input ranges from –20 to 31 dB in steps of 0.1 dB.

The implementation of a digital predistorter (DPD) model that is optimized for HDL code generation and hardware implementation. The predistortion mechanism is executed in two stages. In the first stage, a set of DPD coefficients are estimated based on the input and output data of the power amplifier (PA). In the second stage, the input data of the PA is predistorted based on the estimated DPD coefficients and provided as new input to the PA. This example demonstrates a system-level simulation in which the Digital Predistorter subsystem generates HDL code, while the DPD coefficient estimation generates C/C++ code. This example model supports only Normal and Accelerator simulation modes.

Use the General CRC Generator HDL Optimized block for encoding streaming data according to the 5G NR standard.

Design block interleaver and block deinterleaver blocks and implement interleaving and deinterleaving in a communication system using these blocks.

Implement a WLAN time and frequency synchronization model that is optimized for HDL code generation and hardware implementation. Time and frequency synchronization are the key steps to recover wireless local area network (WLAN) packet information.

Implement DVB-S2 time, frequency, and phase synchronization and PL header recovery using Simulink® blocks that are optimized for HDL code generation and hardware implementation.

Design a wireless local area network (WLAN) receiver that can recover signal and data field information from a WLAN signal. The Simulink® model in this example is optimized for HDL code generation and hardware implementation.

Implement a digital predistorter (DPD) with least mean squares (LMS) based coefficient estimation, which is optimized for HDL code generation and hardware implementation. This example is an extension to the HDL Implementation of Digital Predistorter example for computing DPD coefficients on an FPGA rather than on a processor. This example replaces the C/C++ code generatable RPEM Coeff Estimation subsystem of the HDL Implementation of Digital Predistorter example with an HDL-compatible LMS Coefficient Estimator subsystem. This example supports the hardware-friendly interface for the Xilinx® Zynq® UltraScale™ RFSoC ZCU111 evaluation board, which uses RF data converter. This example model supports Normal and Accelerator simulation modes. For more information about DPD, see Adaptive DPD Design.