HDL-Optimized System Design

Choose algorithms for wireless communications hardware system design

These blocks implement hardware-friendly architectures and support HDL code generation when used with HDL Coder™. The blocks on this page also have streaming interfaces that process a single sample or a vector of samples at a time, hardware control signals, and options to select different hardware implementations of their algorithms.

Blocks

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Block Coding

CCSDS RS Encoder	Encode message into RS codeword according to CCSDS standard
CCSDS RS Decoder	Decode and recover message from RS codeword according to CCSDS standard
DVB-S2 BCH Decoder	Decode and recover message from BCH codeword according to DVB-S2 standard
DVB-S2 LDPC Decoder	Decode LDPC code according to DVB-S2 standard
NR LDPC Encoder	Perform LDPC encoding according to 5G NR standard
NR LDPC Decoder	Decode LDPC code according to 5G NR standard
NR Polar Encoder	Perform polar encoding according to 5G NR standard
NR Polar Decoder	Perform polar decoding according to 5G NR standard
WLAN LDPC Decoder	Decode LDPC code according to WLAN standard
RS Encoder	Encode message to RS codeword
RS Decoder	Decode and recover message from RS codeword

Convolutional Coding

APP Decoder	Decode convolutionally-coded LLR values using MAP algorithm
LTE Convolutional Encoder	Encode binary samples using tail-biting convolutional algorithm
LTE Convolutional Decoder	Decode convolutional-encoded samples using Viterbi algorithm
LTE Turbo Encoder	Encode binary samples using turbo algorithm
LTE Turbo Decoder	Decode turbo-encoded samples
Convolutional Encoder	Encode data bits using convolution coding — optimized for HDL code generation
Puncturer	Punctures data according to puncture vector
Depuncturer	Reverse puncturing scheme to prepare for decoding
Viterbi Decoder	Decode convolutionally encoded data using Viterbi algorithm

Cyclic Redundancy Check (CRC) Coding

LTE CRC Encoder	Generate checksum and append to input sample stream
LTE CRC Decoder	Detect errors in input samples using checksum
NR CRC Encoder	Generate CRC code bits and append them to input data
NR CRC Decoder	Detect errors in input data using CRC

Modulation

DVB-S2 Symbol Demodulator	Demodulate complex constellation symbol to set of LLR values or data bits according to DVB-S2 standard
LTE OFDM Modulator	Modulate LTE resource grid and return time-domain OFDM samples
LTE OFDM Demodulator	Demodulate time-domain OFDM samples and return LTE resource grid
LTE Symbol Modulator	Modulate data bits to complex LTE data symbols
LTE Symbol Demodulator	Demodulate complex LTE data symbols to data bits or LLR values
NR Symbol Modulator	Modulate data bits to complex NR data symbols
NR Symbol Demodulator	Demodulate complex NR data symbols to data bits or LLR values
FFT 1536	Computes fast-fourier-transform (FFT) for LTE standard transmission bandwidth of 15 MHz
OFDM Channel Estimator	Estimate channel using input data and reference subcarriers
OFDM Equalizer	Equalize OFDM data using channel estimates
OFDM Modulator	Modulate frequency-domain OFDM subcarriers to time-domain samples for custom communication protocols
OFDM Demodulator	Demodulate time-domain OFDM samples and return subcarriers for custom communication protocols
Symbol Demodulator	Demodulate complex constellation symbol to set of LLR values or data bits

Utilities

LTE Gold Sequence Generator

Generate Gold sequence

Featured Examples

Sample Rate Conversion for an LTE Receiver

Implement a sample rate converter for an LTE receiver front end.

Open Script

HDL Code Generation for Filtered OFDM (F-OFDM) Transmitter

Filter symbols after the IFFT to improve bandwidth while maintaining orthogonality.

Open Script

HDL Implementation of Variable-Size FFT

Implement a variable-size FFT by using a single FFT core.

Open Script

Accelerate BER Measurement for Wireless HDL LTE Turbo Decoder

The workflow to measure the BER of the Wireless HDL Toolbox™ LTE Turbo Decoder block using parsim to parallelize the simulations across EbNo points. This approach can be used to accelerate other Monte Carlo simulations.

Open Script

HDL Implementation of AWGN Generator

Implement an additive white Gaussian noise (AWGN) generator that is optimized for hardware.

Open Example

HDL Interleaver and Deinterleaver

Design block interleaver and block deinterleaver blocks and implement interleaving and deinterleaving in a communication system using these blocks.

Open Script

Encode Streaming Data Using General CRC Generator HDL Optimized Block for 5G NR Standard

Use the General CRC Generator HDL Optimized block for encoding streaming data according to the 5G NR standard.

Open Script

WLAN HDL Time and Frequency Synchronization

Implement a WLAN time- and frequency-synchronization algorithm that is optimized for hardware.

Open Script

HDL Implementation of WLAN Receiver

Design a wireless local area network (WLAN) receiver that can recover signal and data field information from a WLAN signal. The Simulink® model in this example is optimized for HDL code generation and hardware implementation.

Open Script

HDL Implementation of Digital Predistorter

The implementation of a digital predistorter (DPD) model that is optimized for HDL code generation and hardware implementation. The predistortion mechanism is executed in two stages. In the first stage, a set of DPD coefficients are estimated based on the input and output data of the power amplifier (PA). In the second stage, the input data of the PA is predistorted based on the estimated DPD coefficients and provided as new input to the PA. This example demonstrates a system-level simulation in which the Digital Predistorter subsystem generates HDL code, while the DPD coefficient estimation generates C/C++ code. This example model supports only Normal and Accelerator simulation modes.

Open Example

HDL Implementation of Digital Predistorter with LMS Coefficient Estimation

Implement a digital predistorter (DPD) with least mean squares (LMS) based coefficient estimation, which is optimized for HDL code generation and hardware implementation. This example is an extension to the HDL Implementation of Digital Predistorter example for computing DPD coefficients on an FPGA rather than on a processor. This example replaces the C/C++ code generatable RPEM Coeff Estimation subsystem of the HDL Implementation of Digital Predistorter example with an HDL-compatible LMS Coefficient Estimator subsystem. This example supports the hardware-friendly interface for the Xilinx® Zynq® UltraScale™ RFSoC ZCU111 evaluation board, which uses RF data converter. This example model supports Normal and Accelerator simulation modes. For more information about DPD, see Adaptive DPD Design.

Open Model

DVB-S2 HDL LDPC Encoder

Implement DVB-S2 LDPC encoding using Simulink® blocks that are optimized for HDL code generation.

Open Script

DVB-S2 HDL PL Header Recovery

Implement DVB-S2 time, frequency, and phase synchronization and PL header recovery using Simulink® blocks that are optimized for HDL code generation and hardware implementation.

Open Example

DVB-S2 HDL Receiver

Implement DVB-S2 receiver using Simulink® blocks that are optimized for HDL code generation and hardware implementation.

Open Model