S-R Latch
Behavioral model of an S-R Latch
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Simscape / Electrical / Integrated Circuits / Logic
Description
The S-R Latch block is an abstracted behavioral model of a set-reset latch. It does not model the internal individual MOSFET devices (see Assumptions and Limitations for details). Therefore, the block runs quickly during simulation but retains the correct I/O behavior.
If the gate voltage is greater than the threshold voltage $${V}_{TH}$$, then the input taken is 1
(HIGH
). Otherwise, the input is zero (LOW
). The
gate threshold voltage $${V}_{TH}$$ is halfway between the Low level input voltage ($${V}_{IL}$$) and High level input voltage ($${V}_{IH}$$) parameters.
The block output logic level is either HIGH or LOW, according to the logic levels of the gate inputs and the S-R latch truth table.
S | R | Q _{n} |
---|---|---|
0 | 0 | Q _{n-1} |
0 | 1 | 0 |
1 | 0 | 1 |
1 | 1 | 1 |
The block models the gate as follows:
The gate inputs have infinite resistance and finite or zero capacitance.
The gate output offers a selection of two models:
Linear
andQuadratic
. For more information, see Selecting the Output Model for Logic Blocks. Use the Output current-voltage relationship parameter to specify the output model.You can specify propagation delay for both output models. For
Linear
output, the block sets the value of the gate output capacitor such that the resistor-capacitor time constant equals the Propagation delay parameter value. ForQuadratic
output, the gate input demand is lagged to approximate the Propagation delay parameter value.
The block initial conditions depend on the output model selected:
For
Linear
model, the high initial condition corresponds to the High level output voltage parameter value,V_OH
, and the low initial condition corresponds to the Low level output voltage parameter value,V_OL
.For
Quadratic
model, the high initial condition is a value close to the Supply voltage parameter value,Vcc
, and the low initial condition is close to0
.
The block output voltage depends on the output model selected:
For
Linear
model, output high is the High level output voltage parameter value, and output low is the Low level output voltage parameter value.For
Quadratic
model, the output voltage for High and Low states is a function of the output current, as explained in Quadratic Model Output and Parameters. For zero load current, output high is Vcc (the Supply voltage parameter value), and output low is zero volts.
Assumptions and Limitations
The block does not model the internal individual MOSFET devices that make up the gate
(except for the final MOSFET pair if you select the Quadratic
option for the Output current-voltage relationship parameter). This
limitation has the following implications:
The behavior of this block is abstracted. In particular, response to input noise and inputs that are around the logic threshold voltage can be inaccurate. Also, dynamic response is approximate.
The linear drop in output voltage as a function of output current is an approximation to the MOSFET or bipolar output behavior.
Modeling of the output as a controlled voltage source is representative of a totem-pole or push-pull output stage. To model a device with an open-collector:
Connect the output pin to the base of an NPN Bipolar Transistor or PNP Bipolar Transistor block.
Set the Output resistance parameter to a suitable value.
Ports
Conserving
Parameters
Extended Capabilities
Version History
Introduced in R2009b
See Also
CMOS AND | CMOS Buffer | CMOS NAND | CMOS NOR | CMOS NOT | CMOS OR | CMOS XOR | Schmitt Trigger