FPGA, ASIC 및 SoC 개발

알고리즘 개발부터 하드웨어 설계 및 검증에 이르는 워크플로 자동화

MATLAB^®과 Simulink^®를 사용하여 FPGA, ASIC, SoC 기기에 배포할 프로토타입 및 프로덕션 애플리케이션을 개발합니다. MATLAB과 Simulink를 사용하여 다음을 수행할 수 있습니다.

A four-stage workflow, with the following stages: 1. modeling and simulation, 2. code generation, 3. verification, and 4. deployment.

FPGA, ASIC 및 SoC 개발 관련 제품

Generate Verilog, SystemVerilog, and VHDL code for FPGA and ASIC designs

Find RTL bugs and generate testbenches for ASICs or FPGAs

Prototype and deploy deep learning networks on FPGAs and SoCs

Design and implement wireless communications subsystems for FPGAs, ASICs, and SoCs

Design image processing, video, and computer vision systems for FPGAs and ASICs

Design digital signal processing applications for FPGAs, ASICs, and SoCs

고정소수점 및 부동소수점 알고리즘 모델링 및 최적화

Design, analyze, and deploy hardware/software applications for AMD and Intel SoC devices

Use Simulink Templates for HDL Code Generation (HDL Coder)
Use Simulink model templates for HDL code generation to create efficient hardware designs.
Transmit and Receive Tone Using AMD RFSoC Device - Part 1 System Design (SoC Blockset)
Design and simulate data path using SoC Blockset™ on Xilinx^® RFSoC device.
Wireless Communications Design for ASICs, FPGAs, and SoCs (HDL Coder)
Design wireless communication algorithms for hardware by using Wireless HDL Toolbox™ blocks.
Implement Digital Downconverter for FPGA (DSP HDL Toolbox)
Design a digital downconverter (DDC) for LTE on FPGAs.
Introduction to Custom OFDM (Wireless HDL Toolbox)
This example shows the design and verification of a transmitter and receiver for a custom OFDM communication system that is suitable for HDL code generation. (R2024b 이후)
Convert MATLAB Vision Algorithm to Hardware-Targeted Simulink Model (Vision HDL Toolbox)
Create a hardware-targeted design in Simulink that implements the same behavior as a MATLAB reference design.

Get Started with Simulink HDL Cosimulation (HDL Verifier)
Set up an HDL Verifier™ application using the Cosimulation Wizard in the Simulink® environment.
FPGA-in-the-Loop Simulation (HDL Verifier)
FPGA-in-the-loop (FIL) simulation provides the capability to use Simulink or MATLAB software for testing designs in real hardware for any existing HDL code.
Data Capture Workflow (HDL Verifier)
Capture signal data from a design running on an FPGA.
Access FPGA Memory Using JTAG-Based AXI Manager (HDL Verifier)
Use JTAG-based AXI manager to access memories connected to an FPGA.
UVM Component Generation Overview (HDL Verifier)
Generate a Universal Verification Methodology (UVM) environment from a Simulink model.
Generate SystemVerilog DPI Component (HDL Verifier)
Generate a DPI component from Simulink, and explore various configuration parameters.
Verify Generated Code Using HDL Test Bench from Configuration Parameters (HDL Coder)
Generate a HDL test bench to simulate and verify the generated HDL code for your design.

Basic HDL Code Generation Workflow (HDL Coder)
Follow the workflow for HDL code generation and FPGA synthesis from MATLAB and Simulink algorithms.
Generate IP Core with an AXI4-Stream Interface (HDL Coder)
Use the AXI4-Stream interface to enable high speed data transfer between the processor and FPGA on Zynq^® hardware.
Custom IP Core Generation (HDL Coder)
Generate a custom IP core from a model or algorithm using the HDL Workflow Advisor.
Targeting FPGA & SoC Hardware Overview (HDL Coder)
High-level steps for targeting an FPGA or SoC platform.
Transmit and Receive Tone Using AMD RFSoC Device - Part 2 Deployment (SoC Blockset)
Implement and verify design using SoC Blockset on Xilinx RFSoC device.
Prototype Deep Learning Networks on FPGA and SoC Devices (Deep Learning HDL Toolbox)
Accelerate the prototyping, deployment, design verification, and iteration of your custom deep learning network running on a fixed bitstream by using the dlhdl.Workflow object.