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Run and Verify Generated IP Core

Prototype, simulate, and verify the generated IP core on your target FPGA device

Run and verify the generated bitstream from your IP core design on your target hardware. The input is a generated bitstream for the FPGA portion of your device. The output is a simulated and verified design running on your target FPGA. For more details on the workflow, see Targeting FPGA & SoC Hardware Overview.

Run and Verify IP Core on Target Hardware Workflow

Objects

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fpgaData transfer object to enable data read and write operations from MATLAB to target FPGA or SoC device (Since R2020b)
hdlcoder.DUTPortDUT port from an HDL Coder generated IP core, saved as an object array (Since R2020b)
xilinxsocConnection to processor on Xilinx SoC board to perform basic Linux shell operations or program the board (Since R2022a)
intelsocConnection to processor on Intel SoC board to perform basic Linux shell operations or program the board (Since R2022a)

Functions

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addAXI4SlaveInterfaceWrite data to IP core or read data from IP core using AXI4 or AXI4-Lite interface (Since R2020b)
addAXI4StreamInterfaceWrite data to IP core or read data from IP core using AXI4-Stream interface (Since R2020b)
addMemoryInterfaceAccess memory regions on your FPGA or SoC hardware (Since R2023a)
mapPortMaps a DUT port to specified AXI4 interface in HDL IP core (Since R2020b)
writePortWrite data to a DUT port from MATLAB (Since R2020b)
readPortReads output data and returns it with the port data type and dimension (Since R2020b)
writeMemoryWrite data to memory regions on FPGA or SoC hardware (Since R2023a)
readMemoryRead data from memory regions on FPGA or SoC hardware (Since R2023a)
readMemoryOffsetRead data from memory regions on FPGA or SoC hardware by using offset address (Since R2023b)
writeMemoryOffsetWrite data to memory regions on FPGA or SoC hardware by using the offset address (Since R2023b)
releaseRelease the hardware resources associated with the fpga object (Since R2020b)
systemRun command in Linux shell on SoC board (Since R2022a)
getFileTransfer file from SoC board to host computer (Since R2022a)
putFileTransfer file from host computer to SoC board (Since R2022a)
deleteFileDelete file on SoC board (Since R2022a)
dirList directory contents on SoC board (Since R2022a)
programFPGAProgram FPGA and set corresponding device tree from processor on SoC board (Since R2022a)

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