Choose to Generate HDL Code in Simulink or MATLAB

When deciding how to develop an algorithm from which you want to generate HDL code, you must choose between developing in the Simulink^® or MATLAB^® design environments. MATLAB has a text-based interface that is efficient for rapid algorithm development and prototyping, while Simulink has a graphical interface that enables you to use Model-Based Design to visualize complex systems and manage large designs.

When you use Simulink as your design environment, you can also combine Model-Based Design and MATLAB code by using the MATLAB Function block. For example, you can use Simulink for system-level modeling and MATLAB Function blocks for algorithmic components.

This table compares the strengths of the Simulink and MATLAB design environments. Use this table to determine which design environment meets your design requirements.

Tip

Consider prototyping part of your design in both environments to see if a Simulink or MATLAB works better for your project requirements.

Design Requirements	Simulink Design Environment	MATLAB Design Environment
Example Applications	System-level design across different components and interfaces. Hardware modeling that captures data and control paths and timing. Signal processing chains modeled with single-rate and multirate paths.	Algorithm development with rapid iteration and scripting. Custom logic better expressed as code. High-level synthesis (HLS). For more information, see Get Started with MATLAB to High-Level Synthesis Workflow Using HDL Coder App.
Ease of Use	Enable HDL code modularity and IP integration by organizing the design with Subsystems and Model References. Develop multirate HDL designs by using HDL Coder™ with time-based modeling semantics. Map computations to hardware resources by using supported blocks, tuning block properties, and configuring data types to target registers, LUTs, multiplexers, DSP slices, and RAM. Visualize control and data flow using the modeling environment.	Enable HDL code modularity by using MATLAB functions. Develop multirate HDL designs by pairing a valid control signal with an associated data signal to indicate an active cycle. Map algorithm elements to hardware by using a System object™. For more information, see Hardware Modeling with MATLAB Code. Express complex control flow with MATLAB code. Use MATLAB when many conditional paths might make a block diagram harder to build, read, and maintain.
Simulink Block and MATLAB Language Support	Create models using the Simulink HDL block library. For more information, see hdllib.	Create functions using supported MATLAB functions and features. For more information, see Functions Supported for HDL and HLS Code Generation.
Integration with other MathWorks products	Create models that are compatible with Stateflow® and Simscape™. Create Simulink models that integrate HDL code generation features from the Wireless HDL Toolbox™, DSP HDL Toolbox™, DSP System Toolbox™, and Vision HDL Toolbox™. Use MATLAB code by adding the MATLAB Function block to your models. For more information, see Generate HDL Code from a MATLAB Function Block.	Create MATLAB algorithms that integrate HDL code generation features from the DSP HDL Toolbox, DSP System Toolbox, Vision HDL Toolbox, and Deep Learning HDL Toolbox™.
Optimize Generated HDL Code for Speed and Area	Use a combination of model, subsystem, and block-level speed and area optimizations. For more information, see Speed and Area Optimization.	Use the HDL Coder Optimizations settings for algorithm-level and pragmas for MATLAB statement-level speed and area optimizations. For more information, see Speed and Area Optimization.
Verification and Validation	Verify generated HDL code by generating HDL test benches. For more information, see Verify Generated HDL Code from Simulink Model. If you have HDL Verifier™, you can also: Verify generated HDL code by cosimulating the HDL design. For more information, see HDL Verifier Cosimulation Model Generation in HDL Coder. Verify generated HDL code by loading the code on hardware and running FPGA-in-the-loop simulations. For more information, see FIL Simulation with HDL Workflow Advisor for Simulink (HDL Verifier). Verify generated HDL code with C code generated from the entire Simulink model by using a SystemVerilog DPI test bench. For more information, see Verify HDL Design Using SystemVerilog DPI Test Bench.	Verify generated HDL code by generating HDL test benches. For more information, see Verify Code with HDL Test Bench. If you have HDL Verifier, you can also: Verify generated HDL code by cosimulating the HDL design. For more information, see Verify Sobel Edge Detection Algorithm in MATLAB-to-HDL Workflow. Verify generated HDL code by loading the code into an FPGA board and running FPGA-in-the-loop simulations. For more information, see FIL Simulation with HDL Workflow Advisor for MATLAB (HDL Verifier).
Hardware Deployment and Prototyping	Deploy your design to standalone FPGA boards, system-on-chip (SoC) platforms, or to Simulink Real-Time™ target machines with FPGA I/O boards. To interact with your deployed design on target hardware, use one or more of these methods: Prototype the design from MATLAB by generating MATLAB FPGA I/O host interface scripts. Monitor signals inside the design by using the FPGA Data Capture tool. For a Simulink example leveraging FPGA Data Capture, see Debug IP Core Using FPGA Data Capture. Manually develop the embedded software by creating a generic software interface. Prototype the design from Simulink by generating a Simulink host interface model. Monitor and tune the design and deploy a software model to the processor by creating a Simulink software interface model. Build and deploy an executable independent of MATLAB or Simulink using a Simulink software interface model for standalone applications.	Deploy your design to standalone FPGA boards, system-on-chip (SoC) platforms, or to Simulink Real-Time target machines with FPGA I/O boards. To interact with your deployed design on target hardware, use one or more of these methods: Prototype the design from MATLAB by generating MATLAB FPGA I/O host interface scripts. Monitor signals inside the design by using the FPGA Data Capture tool. For more information on the FPGA Data Capture tool, see FPGA Data Capture (HDL Verifier). Manually develop the embedded software by creating a generic software interface.