Follow instructions for invoking the HDL Workflow Advisor in MATLAB®. See Getting Started with the HDL Workflow Advisor (HDL Coder).
You must have an HDL Coder™ license to generate HDL code using the HDL Workflow Advisor.
Under Select Code Generation Target, make sure
Workflow is set to
Under HDL Verification, select Verify with FPGA-in-the-Loop.
Generate FPGA-in-the-Loop test bench: Select this option to generate a test bench for simulation with FPGA-in-the-loop.
Log outputs for comparison plots: This optional selection lets you log and plot the outputs of the reference design function and the FPGA.
Board Name: Select one of the FPGA development boards. If you have
not yet downloaded an HDL
Verifier™ FPGA board support package, select
Get more boards.
Then return to this step after you have downloaded an FPGA board support package.
FPGA-in-the-Loop Connection: FIL simulation
connection method. The options in the drop-down menu update depending
on the connection methods supported for the target board you selected.
If the target board and HDL
Verifier support the connection, you
Board IP Address and Board MAC Address:
When you select an Ethernet connection, you can adjust the board IP and MAC addresses, if necessary.
|Board IP address|
Use this option for setting the IP address of the board if it is not the default IP address (192.168.0.2).
If the default board IP address (192.168.0.2) is in use by another device, or you need a different subnet, change the Board IP address according to the following guidelines:
|Board MAC address|
Under most circumstances, you do not need to change the board MAC address. If you connect more than one FPGA development board to a single host computer, change the board MAC address for any additional boards so that each address is unique. You must have a separate NIC for each board.
To change the Board MAC address, click in the Board MAC address field. Specify an address that is different from that belonging to any other device attached to your computer. To obtain the Board MAC address for a specific FPGA development board, refer to the label affixed to the board or consult the product documentation.
Enter the names of any additional source files for the DUT. If you have more than one additional source file, use the ... button to add more.
FPGA-in-the-Loop Test Bench Simulation Settings:
If you want the HDL Workflow Advisor to open the FIL simulation, check the box for Simulate generated FPGA-in-the-Loop test bench.
FIL Over Ethernet
FIL Over JTAG
FIL Over PCI Express
If you have not yet run the previous steps, right-click Verify with
FPGA-in-the-Loop and select
Run to Selected Task.
Otherwise, click Run.
This step generates a custom
object™ that provides an interface to your design running on the FPGA board, and generates
a test bench that uses this object to connect to the FPGA board.
If you selected Simulate generated FPGA-in-the-Loop test bench, this step loads the FPGA programming file onto the FPGA, and runs the automatically generated test bench with FPGA-in-the-loop.
If you did not select Simulate generated FPGA-in-the-Loop test bench,
you must load the FPGA programming file manually, using either the customized
function, or the
programFPGA method of the generated object. Reminder: if you have not yet
performed the Guided Hardware Setup or Set Up FPGA Design Software Tools, do so now before loading the programming files.
programFPGA object function:
To run your design on the FPGA board, run the generated test bench, or use the generated object in your own MATLAB code. The first call to the object establishes communication with the FPGA board.