HDL Code Generation and Deployment

Generate HDL code using HDL Coder™, verify code using HDL Verifier™, and prototype designs using hardware support packages

DSP HDL Toolbox™ provides blocks and System objects that support HDL code generation. To generate HDL code from these designs, you must have HDL Coder. HDL Coder also enables you to generate scripts and test benches for use with third-party HDL simulators.

If you have an HDL Verifier license, you can use the FPGA-in-the-loop feature to prototype your HDL design on an FPGA board. HDL Verifier also enables you to cosimulate a Simulink^® model with an HDL design running in a third-party simulator.

To design, prototype, and verify domain-specific practical applications on hardware, download hardware support packages such as SoC Blockset™ Support Package for Xilinx^® Devices and HDL Coder Support Package for Xilinx FPGA and SoC Devices.

Topics

Prototype DSP HDL Algorithms on Hardware
Prototype DSP HDL Toolbox designs on FPGA and SoC boards using hardware support packages.
Verify HDL Design Using SystemVerilog DPI Test Bench (HDL Coder)
This example shows how to use SystemVerilog DPI test bench for verification of HDL code where a large data set is required.

Related Information

HDL Coder
HDL Verifier

Featured Examples

Transmit and Receive Tone Using Xilinx RFSoC Device - Part 1 System Design

Design and simulate data path using SoC Blockset on Xilinx RFSoC device.

Transmit and Receive Tone Using Xilinx RFSoC Device - Part 2 Deployment

Implement and verify design using SoC Blockset on Xilinx RFSoC device.

Polyphase Channelizer

Use the HDL-optimized Channelizer block to process incoming analog-to-digital converter (ADC) samples and produce a spectrum that has 512 MHz of bandwidth. MATLAB® displays the resulting spectrum plot by using FPGA API functions over a TCP/IP connection. The channelizer data sent back is in limited bursts, which are triggered by an AXI4 register in a capture loop. The model also contains an interface to the digital-to-analog converter (DAC) by using a numerically-controlled oscillator (NCO) to drive a tone commanded at some frequency over AXI4.

Multi-Tile Synchronization

Use multi-tile synchronization (MTS) to resolve the time alignment issue of multiple channels across different tiles on an RFSoC device. The RFSoC has built-in features that enforce the time alignment for samples of multiple channels across different tiles. Channels in a tile alone are aligned in time but a guarantee of alignment with another channel from a different tile does not exist. You can enable multi-tile synchronization (MTS) to correct for this issue by first measuring latency across different tiles and then applying sample delays to ensure samples align correctly.