Verification engineers often have to manually recreate many of the MATLAB® models used during system algorithm design. HDL Verifier™ can generate C models wrapped in a SystemVerilog Direct Programming Interface (DPI) for use in Cadence®, Mentor Graphics®, or Synopsys® simulators. Reusing the system algorithm models can save weeks of manual writing and debugging, and these models easily accommodate changes to the specification. This demo shows an FFT checker and waveform generator exported as SystemVerilog DPI-C models and used in a universal verification methodology (UVM) simulation.
You can also select a web site from the following list:
Select the China site (in Chinese or English) for best site performance. Other MathWorks country sites are not optimized for visits from your location.