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Can a Verilog RTL be simulated using Matlab Testbench?
Is there any possibility to co-simulate the verilog RTL and a matlab testbench. If it is possible is there any restrictions for ...
대략 12년 전 | 답변 수: 1 | 0
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Is there any way to convert a verilog code to .m code?
I am doing my M.Tech project in video processing. I am a new user to matlab. I have written a code in verilog. For simulation, t...
대략 12년 전 | 답변 수: 1 | 0
