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HDL Verifier and FPGA in the loop
Hello All, I am trying to use FPGA in the Loop (FIL) using HDL verifier and simulink, but I keep getting the error: Did no...
13년 초과 전 | 답변 수: 8 | 2
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EDA Simulator link and Simulink Cosimulation
Hello All, I am trying to use EDA simulator link with simulink but I am getting the error: Error reported by S...
거의 14년 전 | 답변 수: 3 | 0
