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xiaodong yu


Last seen: 1일 전 |  2023년부터 활동

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Do the additional delays added by adaptive pipeline distroy the alignment between signal paths?
Hi, I want to use adaptive pipeline to optimize the multiply-add module in HDL coder for xilinx FPGA. I enable adaptive piplin...

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HDL Coder reset control
Hi Androw I want to find out all the delay module with "default reset". I use following command, but it is failed. do you have ...

5개월 전 | 0

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mapping lookup table to block ram
I use HDL coder, lookup table block. and enable the option to map look up table to RAM. I have add a piple register right at th...

12개월 전 | 답변 수: 1 | 0

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HDL simulation logic analyzer is slow
my logic analyzer in HDL simulation is slow. can graphic card help on it or adding more grafic memery?

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HDL "complex to Magnitude and angle" module show critical path which can not meet 160MHz clock timing
Hi, experts I try to use the module of "complex to Magnitude and Angle (CMA)" on xilinx FPGA with clock of 160MHz. the critica...

1년 초과 전 | 답변 수: 1 | 0

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timing control module _tc.v have failed path to other module
my HDL code from HDL codeGen has timing error. Some of the failed path are from module _tc.v to other modules. in the tc.v mod...

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wlanhdlreceiver use only 64 sample to do fine symbol timming. is it enough for 40M, 80M and 16MHz wlan signal?
I am learning on the wlanHDLReceiver HDL design. the Design uses 64 data to do fine symbol timing. But in Matlab .m reference de...

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evm demoded from wlan ofdm signal with comm.Phasenoise() increased round 3dB from 80MHz to 160MHz signal bandwidth.
Hi, I am using a comm.Phasenoise to check the phase noise effect on EVM for a demoduation of wlan ofdm signal. the simulation...

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