dr446

2018년부터 활동

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MATLAB as AXI master and FIL tool at the same time
I have a system that requires reading from external ddr3 memory. I also have handwritten verilog code that I want to run using t...

대략 5년 전 | 답변 수: 1 | 0

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Why can I not change the architecture of my subsystem to Black Box?
I am using R2018b. My end goal is to use FPGA in the Loop programming. I have verilog files that I want to include as a black bo...

대략 5년 전 | 답변 수: 3 | 0

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How do I log certain samples only in Simulink?
When my signal crosses a threshold, I would like to write the time the threshold was crossed and the subsystem that it came from...

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Simulink buffer: How do I fix the error "All sample times must be discrete. No continuous or constant sample times are allowed."
I have a discrete scalar input into a simulink buffer and would like the buffer to output a 100x1 vector of the scalar inputs. H...

5년 초과 전 | 답변 수: 3 | 0

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dr446

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