Implementation of a SystemVerilog block in a Simulink simulation

Hello all,

I have a synthesizable SV module that has been tested on an FPGA and as a part of a fabricated IC.

I would like to use this block in a Simulink simulation.

Would appriciate any help\thoughts since I could not find any relevant material online.

Thanks,

Tom

Answer 1

[Kiran Kintali]

https://www.mathworks.com/help/hdlverifier/matlab-cosimulation.html

Consider using cosimulation feature.

You can also integrate customer HDL Code in MATLAB using blackbox features in HDL Coder

https://www.mathworks.com/help/hdlcoder/ref/hdl.blackbox-system-object.html