Simulink HDL-Coder: Vector input External Port
조회 수: 8 (최근 30일)
I want to use vectors as the input for my Simulink Subsystem from which I generate HDL-Coder by using the HDL-Coder. However, this returns errors from the HDL-Coder.
Suppose I have a input signal with 6 boolean values which I group by using a mux (or what . I input them into the HDL-Coder block and use for-each subsystems to do things.
If I want to make the input port to "External Ports", the HDL-Coder throws an error.
Is it possible to use Vectors as the input of the top level sub-system for HDL-Code generation? I can remember that there was a change that made this possible but I am unable to dig this up in the documentation.
Aman Vyas 2020년 12월 15일
Yes there are some blocks which support both vectorisation as well as HDL Code Generation. If those blocks are used within the subsystem for hdl code generation be it be verilog, or VHDL that should work fine without throwing any error in HDL Coder Workflow.
But, if blocks which are used that do not support vectorisations (like HDL Counter) and then if input to them is vectors then in that case they would be throwing error.
Try working with hdllib on commands and then that blocks support hdl code geberation.
Also you can convert bus to vector and vice versa if that helps.