Generating HDL code error in the example "HDL Optimized QPSK Receiver with Captured Data"

조회 수: 5 (최근 30일)
BUMHEE LEE
BUMHEE LEE 2020년 4월 10일
댓글: Kiran Kintali 2020년 4월 18일
I am doing the example for "HDL Optimized QPSK Receiver with Captured Data"(https://www.mathworks.com/help/comm/examples/hdl-optimized-qpsk-receiver-with-captured-data.html)
and got a below message.
1) Generating DUT using verilog was successful. (Default language was set to VDHL)
2) Generating Test bench was failed.
How can I fix it? Could you help me?

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답변 (1개)

Kiran Kintali
Kiran Kintali 2020년 4월 12일
This is a bug in HDL test bench generation. Please reach out to support@mathworks.com with reproduction steps.

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