Importing hdl code changes signal type, and it's super annoying to convert it back for sim

Hi,

I have a very simple VHDL module that I have imported into Simulink using the DSP Builder/HDL coder toolbox. Here's the port definition:

entity trigen is
  port (
    clock : in std_logic; -- Assuming 50mhz operation
    triout : out unsigned(12 DOWNTO 0)
  );
end entity;

triout just produces a simple triangle wave that I want to see on a Scope. However, HDL Import forces the output of this block to an INT13 instead of an unsigned value. The scope then tries to convert this value into a double, and thinks its looking at a 2's compliment number.

Using a simple type conversion does not work since it will change the data assuming you want to convert over from 2's comp.

How do I 'cast' the type, or fix the import?

Thank you :)

Answer 1

[Kiran Kintali]

can you share the vhdl file and the version of MATLAB and HDLCoder used for hdlimport?

thanks

[TheGreatNed]

VHDL file attached

MATLAB 2018a

I don't know the hdlcoder version.... DSP Builder is linked with my 16.1 version of Quartus Prime

Edit: The attached VHDL file I changed trigen to be 16 bits instead of the desired 13 bits for testing purposes, but the problem is still fundamentally the same (ie, HDL coder imports it as a signed value, and there is no easy way to cast it back to uint16)