Fix point problem in FPGA

Sir,

I have Cyclone FPGA kit (EP1C12Q240C8) {with a interfacing card made by IISC Bangalore}, Matlab 2011b (and Matlab 2012a), Modelsim 10.0c SE, Altera Quartus II (11.0sp1) Web Edition (i.e free version), OS: Windows Xp sp2 (32bit)

Back ground of difficulties:

1. I cannot use this kit by MATLAB directly as "FPGA-in-the-loop" and "FPGA Turnkey workflow" does not support Altera Cyclone FPGA family.

(Ref: http://www.mathworks.in/matlabcentral/answers/49201-is-it-possible-to-work-with-altera-cyclone-ep1c12q240c8-fpga-kit-and-matlab-hdl-workflow-advisor )

2. FPGA requires fixpoint variable values.

(Ref: http://www.mathworks.in/matlabcentral/newsreader/view_thread/322546#887877 )

Problems:

now in simulink *.mdl file, I create a simple add two number model:

one constant block having value 4 with fixdt(0,12)

another constant block having value 5 with fixdt(0,12)

sum block with fixdt(0,13), min value =4 and Max value =9

In "compare scope windows" in simulink both result is 9 but in co-simulation (modelsim) wave format and also in Quartus (9.1) it is showing 576 (in unsigned format view I select)

When the values are real (format in simulink "double" )then modelsim is showing same result as in simulink compare scope windows (but FPGA requires fix point) I cannot understand why it is showing "576" instead of "9".

HDL code is :

LIBRARY IEEE; 
USE IEEE.std_logic_1164.ALL; 
USE IEEE.numeric_std.ALL;
ENTITY Addkm IS PORT( R : OUT std_logic_vector(12 DOWNTO 0) -- ufix13_En6 ); END Addkm;
ARCHITECTURE rtl OF Addkm IS
-- Signals
SIGNAL A_out1                           : unsigned(11 DOWNTO 0);  -- ufix12_En9
SIGNAL B_out1                           : unsigned(11 DOWNTO 0);  -- ufix12_En9
SIGNAL Sum_add_cast                     : unsigned(12 DOWNTO 0);  -- ufix13_En9
SIGNAL Sum_add_cast_1                   : unsigned(12 DOWNTO 0);  -- ufix13_En9
SIGNAL Sum_add_temp                     : unsigned(12 DOWNTO 0);  -- ufix13_En9
SIGNAL Sum_out1                         : unsigned(12 DOWNTO 0);  -- ufix13_En6
BEGIN A_out1 <= to_unsigned(2048, 12);
B_out1 <= to_unsigned(2560, 12);
Sum_add_cast <= resize(A_out1, 13);
Sum_add_cast_1 <= resize(B_out1, 13);
Sum_add_temp <= Sum_add_cast + Sum_add_cast_1;
Sum_out1 <= resize(Sum_add_temp(12 DOWNTO 3), 13);
R <= std_logic_vector(Sum_out1);
END rtl;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Would anyone like to help me regarding this subject

With Regards Kingsuk

[Kingsuk]

would anyone like to give me a way to die out this problem ...