Delay Balancing Error (RTL Code/ IP Core generation)

Hallo everybody

I am using MATLAB/SIMULINK and HDL Coder to generate and IP Core for the ZedBoard DevKit.

I am encountering an issue with the "Delay Balancing" option. Basically SIMULINK got stuck during the HDL Code generation with the following error message:

“Error Delay balancing unsuccessful because Delay introduced in feedback loop cannot be path balanced. Offending Block: ....../Trigonometric Function”

1. Could someone please explain me the reason why this is happening ?

2. Could someone please explain me what should I do to avoid this situation?

I find a workaround for this issue. I have done the following changes:

- I put the "Trigonometric Fucntion" blocks into a subsystem (called "Trigonometric Fcn")

- I have disabled the "BalanceDelays" option from the HDL Coder properties

- I have set to "OFF" the "BalanceDelays" option for the "TOP" subsystem of the model

- I have left set to "Inherit" the "BalanceDelays" option for the other subsystems of the model

- but I have set to "ON" the "BalanceDelays" option for the "Trigonometric Fcn" subsystems of the model

- I have generated the "Validation Model" and I have verified that the results match the original one

This allow me to generate the HDL code and continue to the creation of the IP Core and the Vivado project.

But I would like to keep the BalanceDelays option "ON" otherwise the HDL code won't be optimised in terms of area and timing performance.

3. Could someone please give me the correct solution to this error?

I am sorry, but I cannot share the code otherwise I would attached the model and other useful information.

Thank you in advance,

Andrea Foradori

[FPGA User]

Barry, just to confirm, HDL coder will require disabling delay balancing if the model containts introduced delays inside a feeback loop.

[Kiran Kintali]

Disabling delay balancing is not recommended.

If you have stable paths (input signals that do not change after reset time such as filter coeffients) that need not be balanced you can use the port level option to turn off delay balancing on those paths.

https://www.mathworks.com/help/hdlcoder/ug/delay-balancing.html

In all other usecases you need to allocate the latency budget required for the feedback loop with design delays or use clock rate pipelining (by enabling oversampling) to accomadate delay balancing of those feedback paths.

Answer 1

[Kiran Kintali]

https://www.mathworks.com/help/hdlcoder/ug/delay-balancing.html

You need to work towards not introduce delays in feedback loops, or manually add design delays and balance/handle delays in the loop.

https://www.mathworks.com/help/hdlcoder/ug/clock-rate-pipelining.html

If your design has a budget for OverSampling (typical control system designs have such affordance huge ratio between clock rate in MHz and data rate in KHz) set the OverSampling factor on the model and let HDLCoder use the budget to do clock rate pipelining and balance delays in feedback loops.