Error in conversion of simulink model into verilog code?

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SUKUMAR NAGINENI
SUKUMAR NAGINENI 2019년 3월 17일
답변: Kiran Kintali 2019년 3월 17일
Hello,
We are getting an error while conversion of Simulink model into Verilog code using HDL coder. Anyone can resolve this problem.
The details of the current MATLAB version and the error attached below.
MATLAB 2015 b (32-bit).
p.JPG

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Kiran Kintali
Kiran Kintali 2019년 3월 17일
Absence of the necessary files shows you seem to have installation issues.
Can you please do a clean reinstall and if it doesn't help can you contact MathWorks install team support?
Thanks

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