Empty objectives in Design Verifier
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I created a model in Simulink and i wished to prove a property using Design Verifier.
Here is a portion of the model:


The verification system is the following:

Design Verifier analysis starts correctly, but it tries to validate 27 objectives instead of 1 (it seems one for each output message in the chart above)

Also those objectives seem to be empty.
Is there a way to validate only my objective?
댓글 수: 5
Pat Canny
2019년 3월 10일
Hi Lorenzo,
The images of your model are not showing - perhaps it's my browser.
Can you try inserting the images again?
Thanks.
Lorenzo Niccolai
2019년 3월 10일
Pat Canny
2019년 3월 12일
Does your model have any Assertion blocks or other blocks from the Model Verification library? Design Verifier treats those blocks as proof objectives by default.
To disable this, change the Assertion blocks setting in the Design Verifier Pane: Property Proving: https://www.mathworks.com/help/sldv/ug/design-verifier-pane-property-proving.html
If you want to disable all Assertion blocks, select "Disable all". If you want to manually enable or disable certain blocks, select "Use local settings".
This can also be done via the DVAssertions parameter in the sldvoptions function: https://www.mathworks.com/help/sldv/ug/simulink-design-verifier-configuration-parameters.html
Lorenzo Niccolai
2019년 3월 14일
Pat Canny
2019년 3월 18일
Hi Lorenzo,
This likely requires further digging. I don't know if we'll solve this via MATLAB Answers.
Do you mind contacting MathWorks Support? https://www.mathworks.com/support/contact_us.html?s_tid=sp_ban_cs
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