I would like to know about why we need to convert our data to logical with serializer when we use AXI4-Stream interfaces. I want to use 32-bit width data in/out instantly to my DUT block.
In HDL Coder User Guide, i saw these descriptions below;
"• Connect each DUT input vector data port to a Serializer1D block.
The Serializer1D block must have a ValidOut port and the Ratio set to the vector bit
This situation forces me to use 1-bit flow design in my IP block. So I am getting inefficient design, while i need some speed. Is there any workaround or explanation about this?