Settings for fixed clock naming in Simple Dual Port RAM generation?

Depending on my generation settings, the clock naming conventions may vary in generated verilog for Simple Dual Port Ram blocks.

For instance, in one design, the DPRam has a clock port named simply, "clk". However, in a separate design which uses multiple clocks, the DPRam clock port gets the name "clk_1_16". The file names remain identical, however: "simpleDualPortRam_Wrapper_generic.v" and "simpleDualPortRam_Wrapper_generic.v".

As a result, when building my setup in the Xilinx Vivado environment, there will be a conflict between the multiple simpleDualPortRam_Wrapper_generic.v files with multiple clock port names.

Is there some way to either name the verilog files in accordance with the chosen block name internal to the model? Or if the files are going to be called "...generic", could they maintain a generic port naming convention?

Answer 1

[Kiran Kintali]

It looks like you are using 'ClockInputs', 'Multiple' option in HDL Coder that leads to generation of logic with Multiple Clocks. See the attached example with different rates in the model and generated code using multiple clocks option.

>> makehdl('MultipleClocksSqrt/DUT1', 'ClockInputs', 'Multiple')

Look for the following comment in the top of the generate DUT file explaining Clock Naming in Module_A, _B and _C.vhd files.

Please share your RAM model and we can take a look at your file reuse issue.

HDL Coder avoids name collisions with a single code generation process. If you have name collisions between code generation for two different DUTs or different Models, consider use of ModulePrefix parameter during code generation.